FinFET device with high-k metal gate stack

• US 10,468,528 B2
• Filed: 04/16/2014
• Issued: 11/05/2019
• Est. Priority Date: 04/16/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Fung, Ka-Hing, Chang, Chih-Sheng, Wu, Zhiqiang
• Primary Examiner(s): Gebremariam, Samuel A
• Assistant Examiner(s): Beardsley, Jonas T
• Application Number:
  US14/254,035
• Publication Number:
  US 20150303305A1
• Time in Patent Office: 2,029 Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region.

Claims

1. A device, comprising:

a substrate having a gate region and source/drain (S/D) regions separated by the gate region;

a first fin structure over the substrate and in the gate region, the first fin structure including a lower portion and an upper portion over the lower portion, wherein;

the lower portion includes a portion of a first semiconductor material layer as its inner layer and a portion of a semiconductor oxide layer as its outer layer, wherein the first semiconductor material layer has a first width and the semiconductor oxide layer has a second width, the first semiconductor material layer and the semiconductor oxide layer have a same thickness, the semiconductor oxide layer is wider in its center portion than its top and bottom portions, and the semiconductor oxide layer includes oxygen and material of the first semiconductor material layer; and

the upper portion includes a portion of a second semiconductor material layer, wherein the second semiconductor material layer has a third width, which is smaller than the first width;

a high-k (HK)/metal gate (MG) stack on the substrate and wrapping around a portion of the first fin structure in the gate region;

epitaxial S/D layers in the S/D regions, wherein the semiconductor oxide layer extends under the epitaxial S/D layers for a full length of the epitaxial S/D layers; and

a second fin structure in the S/D regions and under the epitaxial S/D layers, the second fin structure including a second lower portion and a second upper portion over the second lower portion, wherein;

the second lower portion of the second fin structure includes another portion of the first semiconductor material layer as its inner layer and another portion of the semiconductor oxide layer as its outer layer;

the second upper portion of the second fin structure includes another portion of the second semiconductor material layer and the second upper portion of the second fin structure is between the second lower portion of the second fin structure and a bottom surface of the epitaxial S/D layers.

2. The device of claim 1, wherein the second width is in a range of 10% to 30% of the first width.

3. The device of claim 1, wherein the third width is less than 75% of the first width.

4. The device of claim 1, wherein the portion of the first fin structure wrapped around by the HK/MG has a height in a range of 20 nm to 40 nm.

5. The device of claim 1, wherein the first semiconductor material layer includes silicon germanium (SiGex), where x is Ge composition in atomic percent.

6. The device of claim 5, wherein a center portion of the first semiconductor material layer has a higher Ge composition x than other portions of the first semiconductor material layer.

7. The device of claim 6, wherein the Ge composition of the center portion is 5% to 30% higher than the other portions.

8. The device of claim 1, wherein the semiconductor oxide layer includes SiGeOy, where y is oxygen composition in atomic percent.

9. The device of claim 1,

wherein the epitaxial S/D features are directly above at least a portion of the semiconductor oxide layer.

10. The device of claim 1, further comprising:

an isolation layer, wherein an upper surface of the isolation layer is below an uppermost surface of the upper portion of the first fin structure and above a lowermost surface of the upper portion of the first fin structure.

11. A device, comprising:

a substrate having a gate region and source and drain (S/D) regions separated by the gate region;

a first fin structure in the gate region, the first fin structure including a lower portion and an upper portion over the lower portion, wherein;

the lower portion of the first fin structure includes a portion of a silicon germanium (SiGex) layer as its inner layer and a portion of a silicon germanium oxide (SiGeOy) layer as its outer layer, where x is Ge composition in atomic percent and y is oxygen composition in atomic percent, wherein the SiGex layer has a first width and the SiGeOy layer has a second width, the SiGex layer and the SiGeOy layer have a same thickness; and

the upper portion of the first fin structure includes a portion of a Si layer, wherein the Si layer has a third width, which is smaller than the first width;

a second fin structure in the S/D regions, the second fin structure including a second lower portion and a second upper portion over the second lower portion, wherein;

the second lower portion of the second fin structure includes another portion of the silicon germanium (SiGex) layer as its inner layer and another portion of the silicon germanium oxide (SiGeOy) layer as its outer layer; and

the second upper portion of the second fin structure includes another portion of the Si layer;

epitaxial source/drain layers over the second upper portion of the second fin structure in the S/D regions and directly above at least a portion of the SiGeOy layer, wherein a bottom surface of the epitaxial source/drain layers is above the second upper portion of the second fin structure; and

a high-k/metal gate (HK/MG) over the substrate and wrapping around a portion of the first fin structure in the gate region.

12. The device of claim 11, wherein the second width is in a range of 10% to 30% of the first width.

13. The device of claim 11, wherein the third width is less than 75% of the first width.

14. The device of claim 11, wherein a center portion of the SiGex layer has a higher Ge composition x than other portions of the SiGex layer.

15. The device of claim 14, wherein the Ge composition x of the center portion of the SiGex layer is 5% to 30% higher than the other portions of the SiGex layer.

16. The device of claim 11, further comprising:

an isolation layer, wherein a top surface of the isolation layer is above a top surface of the lower portion of the first fin structure, and below a top surface of the upper portion of the first fin structure, and wherein the top surface of the isolation layer is above both a top surface of the second lower portion of the second fin structure and a top surface of the second upper portion of the second fin structure.

17. The device of claim 11, wherein the silicon germanium oxide layer is wider in its center portion than its top and bottom portions.

18. A semiconductor device, comprising:

a substrate;

a first fin structure over the substrate, the first fin structure including a lower portion and an upper portion over the lower portion, wherein;

the lower portion includes a portion of a first semiconductor material layer as its inner layer and a portion of a semiconductor oxide layer as its outer layer, wherein the first semiconductor material layer has a first width and the semiconductor oxide layer has a second width that is less than the first width, the first semiconductor material layer and the semiconductor oxide layer have a same thickness, the semiconductor oxide layer is wider in its center portion than its top and bottom portions, and the semiconductor oxide layer includes oxygen and material of the first semiconductor material layer; and

the upper portion includes a portion of a second semiconductor material layer, wherein the second semiconductor material layer has a third width that is less than the first width;

a high-k (HK)/metal gate (MG) stack over the substrate and wrapping around a portion of the first fin structure; and

two epitaxial source/drain layers on two opposing sides of the HK MG stack and directly above at least a portion of the first semiconductor material layer, wherein the semiconductor oxide layer extends a full length of the at least the portion of the first semiconductor material layer, wherein an entirety of the two epitaxial source/drain layers is above the second semiconductor material layer.

19. The semiconductor device of claim 18, wherein the second width is in a range of 10% to 30% of the first width and the third width is less than 75% of the first width.

20. The semiconductor device of claim 18, wherein the first semiconductor material layer includes silicon germanium (SiGex), where x is Ge composition in atomic percent, and wherein a center portion of the first semiconductor material layer has a higher Ge composition x than other portions of the first semiconductor material layer.