Method for fabricating semiconductor device

• US 10,468,538 B1
• Filed: 07/17/2018
• Issued: 11/05/2019
• Est. Priority Date: 07/17/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Chih-Haw, Chen, Tzu-Ping
• Primary Examiner(s): Mehta, Ratisha
• Application Number:
  US16/038,068
• Time in Patent Office: 476 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

A method for fabricating semiconductor device includes providing a substrate having a first device region and a second device region. Floating gate structure is formed in the first device region. Liner layer and nitride layer are sequentially deposited over the first device region and the second device region. The floating gate structure is conformally covered. Etching back process is performed on the nitride layer to reduce thickness of the nitride layer. The first device region is still covered by the nitride layer. A photomask layer is formed over the substrate with an opening region to expose the second device region for cleaning. The photomask layer is removed. A gate oxide layer grows on the substrate in the second device region. Anisotropic etching process is performed to remove the nitride layer, resulting in a nitride spacer on a lower portion of a sidewall of the floating gate structure.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a first device region and a second device region;

forming a floating gate structure in the first device region;

sequentially depositing a liner layer and a nitride layer over the first device region and the second device region, wherein the floating gate structure is conformally covered by the liner layer and the nitride layer;

performing an etching back process on the nitride layer to reduce a thickness of the nitride layer, wherein the first device region is still covered by the nitride layer;

forming a photomask layer over the substrate with an opening region to expose the second device region;

cleaning the second device region;

removing the photomask layer;

growing a gate oxide layer on the substrate in the second device region; and

performing an anisotropic etching process to remove the nitride layer, resulting in a nitride spacer on a lower portion of a sidewall of the floating gate structure.

2. The method for fabricating semiconductor device in claim 1, wherein the step of forming the floating gate structure comprises:

forming a tunnel oxide layer on the substrate;

forming a polysilicon layer on the oxide layer;

forming a silicon nitride layer on the polysilicon layer, wherein the silicon nitride layer has an opening at the first device region;

forming a polysilicon oxide on the polysilicon layer in the opening; and

removing the silicon nitride layer, the polysilicon layer and the tunnel oxide layer, wherein a portion of the polysilicon layer and the tunnel oxide layer under the polysilicon oxide remains to form the floating gate structure.

3. The method for fabricating semiconductor device in claim 1, wherein the nitride layer after the etching back process remains fully covering the floating gate structure at the first device region.

4. The method for fabricating semiconductor device in claim 1, wherein the gate oxide layer on the substrate as grown in the second device region is a part of the input/output transistor, which is to be operated by an input/output voltage in a range of 4V to 7V.

5. The method for fabricating semiconductor device in claim 1, wherein in the step of performing the anisotropic etching process, the nitride layer is an exposed state in first device region, an etchant with etching selection ratio to nitride is used to remove the nitride layer.

6. The method for fabricating semiconductor device in claim 1, wherein the step of performing the anisotropic etching process comprises using an etching mask layer to cover the second device region while the nitride layer is etched.

7. The method for fabricating semiconductor device in claim 1, further comprising performing an implanting process to dope the substrate to form a doped well at a predetermined position in the second device region.

8. The method for fabricating semiconductor device in claim 1, wherein the step of growing the gate oxide layer comprises a thermal oxidation process, wherein a polysilicon material of the floating gate structure in the first device region remains a protection by the nitride layer to resist the thermal oxidation process.

9. The method for fabricating semiconductor device in claim 1, wherein the lower portion of the sidewall of the floating gate structure for forming the nitride spacer is equal to or less than ⅓

of the sidewall of the floating gate structure.

10. The method for fabricating semiconductor device in claim 1, wherein the floating gate structure comprises a floating polysilicon layer and a tunnel oxide layer, sequentially stacked on the substrate, wherein the tunnel oxide layer has a central region thickness and an edge thickness, and a thickness ratio of the edge thickness to the central region thickness is in a range of less than or equal to 1.7 and greater than 1.

11. The method for fabricating semiconductor device in claim 10, wherein the step of growing the gate oxide layer also oxidizes the floating polysilicon layer at an edge region to have the edge thickness.

12. The method for fabricating semiconductor device in claim 10, wherein the thickness ratio is in a range of 1.6 to 1.2.

13. A floating gate structure of semiconductor device, comprising:

a floating gate structure on a substrate, wherein the floating gate structure comprises;

a tunnel oxide layer on the substrate;

a polysilicon layer on the tunnel oxide layer; and

a polysilicon oxide layer on the polysilicon layer;

a liner oxide layer on the substrate covering the floating gate structure; and

a nitride spacer, on the liner oxide layer at a lower portion of a sidewall of the floating gate structure,

wherein the tunnel oxide layer has a central region thickness and an edge thickness, and a thickness ratio of the edge thickness to the central region thickness is in a range of equal to or less than 1.7 and greater than 1.

14. The floating gate structure in claim 13, wherein the thickness ratio is in a range of 1.6 to 1.2.

15. The floating gate structure in claim 13, wherein the nitride spacer is less than ⅓

of a sidewall of the floating gate structure.