Magnetoresistance element and non-volatile semiconductor storage device using same magnetoresistance element

• US 10,468,591 B2
• Filed: 12/09/2016
• Issued: 11/05/2019
• Est. Priority Date: 09/17/2009
• Status: Active Grant

• Current Assignee: III Holdings 3, LLC
• Original Assignee: III Holdings 3, LLC
• Inventors: Yamada, Michiya, Ogimoto, Yasuchi
• Primary Examiner(s): Nguyen, Hien N
• Application Number:
  US15/374,605
• Publication Number:
  US 20170092853A1
• Time in Patent Office: 1,061 Days
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

The invention provides a magnetoresistance element with a configuration such that a stable switching action is possible with a current flowing in response to the application of a unipolar electrical pulse, and a non-volatile semiconductor storage device using the magnetoresistance element.

A magnetoresistance element 1-1 includes a magnetic tunnel junction portion 13 configured by sequentially stacking a perpendicularly magnetized first magnetic body 22, an insulation layer 21, and a perpendicularly magnetized second magnetic body 200. The second magnetic body 200 has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer 21 side interface. A heat assist layer 28-1 that heats the second magnetic body 200 with a heat generated based on a current flowing through the magnetic tunnel junction portion 13 is further provided, and the magnetization direction of the second magnetic body 200 is reversed by the heating of the second magnetic body 200. A non-volatile semiconductor storage device 10-1 includes the magnetoresistance element 1-1, a switching element connected in series to the magnetoresistance element 1-1, information rewriting means that carries out a write and erase by causing a write current to flow through the magnetoresistance element 1-1, and reading means that reads information stored from the amount of current flowing through the magnetoresistance element 1-1.

Claims

1. A method comprising:

forming a pinned layer, an insulation layer, and a storage layer;

forming a heat assist layer above the storage layer using reactive sputtering; and

forming an upper electrode above the heat assist layer using magnetron sputtering, wherein the pinned layer, the insulation layer, and the storage layer are formed using magnetron sputtering.

2. The method of claim 1, wherein the heat assist layer comprises TaN.

3. The method of claim 1, further comprising forming a protective layer between the storage layer and the heat assist layer.

4. The method of claim 3, wherein the protective layer comprises at least one of Ta or Ru.

5. The method of claim 1, further comprising:

forming a resist above the upper electrode;

subsequently removing material not below the resist;

subsequently removing the resist;

subsequently forming interlayer insulation above the upper electrode;

subsequently forming a hole in the interlayer insulation above the upper electrode; and

subsequently forming a contact in the hole, such that the contact abuts the upper electrode.

6. The method of claim 5, wherein said removing material not below the resist comprises using ion etching.

7. The method of claim 5, wherein said forming a hole in the interlayer insulation comprises using photolithography.

8. The method of claim 1, wherein:

the pinned layer is formed above a lower electrode; and

the lower electrode is formed above a portion of a CMOS transistor.

9. The method of claim 8, wherein the portion of the CMOS transistor comprises a drain region.

10. A method comprising:

forming a heat assist layer using magnetron sputtering;

above the heat assist layer, forming a pinned layer, an insulation layer, and a storage layer; and

forming an upper electrode above the storage layer using magnetron sputtering, wherein the pinned layer, the insulation layer, and the storage layer are formed using magnetron sputtering.

11. The method of claim 10, wherein the heat assist layer comprises TaN.

12. The method of claim 10, further comprising:

forming a resist above the upper electrode;

subsequently removing material not below the resist;

subsequently removing the resist;

subsequently forming interlayer insulation above the upper electrode;

subsequently forming a hole in the interlayer insulation above the upper electrode; and

subsequently forming a contact in the hole, such that the contact abuts the upper electrode.

13. The method of claim 12, wherein said removing material not below the resist comprises using ion etching.

14. The method of claim 12, wherein said forming a hole in the interlayer insulation comprises using photolithography.

15. The method of claim 10, wherein:

the pinned layer is formed above a lower electrode; and

the lower electrode is formed above a portion of a CMOS transistor.

16. The method of claim 15, wherein the portion of the CMOS transistor comprises a drain region.