Code synchronization for analog spread spectrum systems

• US 10,469,126 B1
• Filed: 09/24/2018
• Issued: 11/05/2019
• Est. Priority Date: 09/24/2018
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Kilambi, Sai Mohan, Bowles, Gregory John, Hu, Lan, Ho, Tan Huy
• Primary Examiner(s): Tadese, Berhanu
• Application Number:
  US16/140,156
• Time in Patent Office: 407 Days
• Field of Search: None
• CPC Class Codes: H04B 1/7073 Synchronisation aspects
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 7/2637 for logical channel control
• CPC Class Codes: H04J 13/0074 Code shifting or hopping

Abstract

Methods and apparatuses for performing synchronization in a receiver of an analog code division spreading system are described. The method includes outputting a sampling point alignment signal to apply first time delays to align encoder code signals with a sampling point of an ADC The ADC is used to obtain digital samples of the orthogonal code-encoded analog signal at the sampling point. The method also includes outputting a decoder code alignment signal to apply second time delays to align decoder code signals with the digital samples. The method also includes outputting an orthogonal code alignment signal to apply third time delays to the decoder code signals and the encoder code signals, to maintain mutual orthogonality among the decoder code signals and to maintain mutual orthogonality among the encoder code signals.

Claims

1. A method for performing synchronization in a receiver of an analog code division spreading system, the method comprising:

outputting at least one sampling point alignment signal to apply one or more determined first time delays to encoder code signals, the encoder code signals carrying encoder codes used by an encoder for generating an orthogonal code-encoded analog signal, the one or more first time delays being determined to align the encoder code signals with a sampling point of an analog-to-digital converter (ADC), the ADC being used to obtain digital samples of the orthogonal code-encoded analog signal at the sampling point;

outputting at least one decoder code alignment signal to apply one or more determined second time delays to decoder code signals, the decoder code signals carrying decoder codes used by a decoder for decoding the digital samples, the one or more second time delays being determined to align the decoder code signals with the digital samples; and

outputting at least one orthogonal code alignment signal to apply one or more determined third time delays to the decoder code signals and the encoder code signals, the one or more third time delays being determined to maintain mutual orthogonality among the decoder code signals and to maintain mutual orthogonality among the encoder code signals.

2. The method of claim 1, further comprising:

outputting a phase shift signal to control the ADC to obtain the digital samples at a determined sampling point.

3. The method of claim 2, wherein the determined sampling point is determined by:

obtaining sign samples of digital samples of a known orthogonal code-encoded analog signal, the known orthogonal code-encoded analog signal being generated by encoding a known analog signal with a known encoder code; and

determining the sampling point by outputting the phase shift signal to adjust the sampling point for obtaining the digital samples until the obtained sign samples match expected signs of the known encoder code.

4. The method of claim 3, wherein the known analog signal is a substantially constant analog signal.

5. The method of claim 3, wherein the known encoder code has a fastest code rate among the encoder codes.

6. The method of claim 1, wherein at least one of the one or more first time delays is determined by:

obtaining sign samples of digital samples of a known orthogonal code-encoded analog signal, the known orthogonal code-encoded analog signal being generated by encoding a known analog signal with a known encoder code; and

determining the at least one first time delay by adjusting time delay applied to a signal carrying the known encoder code until the obtained sign samples match expected signs of the known encoder code.

7. The method of claim 6, wherein the at least one first time delay comprises a plurality of first time delays, and the plurality of first time delays are determined, in series, for a respective plurality of signals carrying respective known encoder codes.

8. The method of claim 1, wherein at least one of the one or more second time delays is determined by:

obtaining sign samples of digital samples of a known orthogonal code-encoded analog signal, the known orthogonal code-encoded analog signal being generated by encoding a known analog signal with a known encoder code; and

determining the at least one second time delay by performing a cyclic cross correlation calculation to determine a relative shift between the obtained sign samples and the expected signs of the known decoder code, and determining the at least one second time delay to compensate for the relative shift.

9. The method of claim 8, wherein the at least one second time delay comprises a plurality of second time delays, and the plurality of second time delays are determined, in series, for a respective plurality of known decoder codes.

10. The method of claim 1, wherein the at least one third time delay is determined for achieving mutual orthogonality between decoder code signals having same sign rates.

11. An apparatus for performing synchronization in a receiver of an analog code division spreading system, the apparatus comprising:

a synchronizer configured to;

receive, from an analog-to-digital converter (ADC), digital samples of an orthogonal code-encoded analog signal, the digital samples being obtained by the ADC at a sampling point;

output at least one sampling point alignment signal to apply one or more determined first time delays to encoder code signals, the encoder code signals being used by an encoder for generating the orthogonal code-encoded analog signal, the one or more first time delays being determined to align the encoder code signals with the sampling point of the ADC;

output at least one decoder code alignment signal to apply one or more determined second time delays to decoder code signals, the decoder code signals being used by a decoder for decoding the digital samples, the one or more second time delays being determined to align the decoder code signals with the digital samples; and

output at least one orthogonal code alignment signal to apply one or more determined third time delays to the decoder code signals and the encoder code signals, the one or more third time delays being determined to maintain mutual orthogonality among the decoder code signals and to maintain mutual orthogonality among the encoder code signals.

12. The apparatus of claim 11, wherein the synchronizer is further configured to:

output a phase shift signal to control the ADC to obtain the digital samples at a determined sampling point.

13. The apparatus of claim 12, wherein the synchronizer comprises a sign sampler, and wherein the synchronizer is further configured to determine the determined sampling point by:

obtaining, by the sign sampler, sign samples of digital samples of a known orthogonal code-encoded analog signal, the known orthogonal code-encoded analog signal being generated by encoding a known analog signal with a known encoder code; and

determining the sampling point by outputting the phase shift signal to adjust the sampling point for obtaining the digital samples until the obtained sign samples match expected signs of the known encoder code.

14. The apparatus of claim 11, wherein the synchronizer comprises a sign sampler, and wherein the synchronizer is further configured to determine at least one first time delay by:

obtaining, by the sign sampler, sign samples of digital samples of a known orthogonal code-encoded analog signal, the known orthogonal code-encoded analog signal being generated by encoding a known analog signal with a known encoder code; and

determining at least one first time delay by adjusting time delay applied to a signal carrying the known encoder code until the obtained sign samples match expected signs of the known encoder code.

15. The apparatus of claim 11, wherein the synchronizer comprises a sign sampler, and wherein the synchronizer is further configured to determine at least one second time delay by:

obtaining, by the sign sampler, sign samples of digital samples of a known orthogonal code-encoded analog signal, the known orthogonal code-encoded analog signal being generated by encoding a known analog signal with a known encoder code; and

determining at least one second time delay by performing a cyclic cross correlation calculation to determine a relative shift between the obtained sign samples and the expected signs of the known decoder code, and determining the at least one second time delay to compensate for the relative shift.

16. The apparatus of claim 11, further comprising a decoder configured to decode the digital samples, using the decoder code signals.

17. The apparatus of claim 16, further comprising one or more decoder delay adjustment blocks, wherein the synchronizer is configured to output the at least one decoder code alignment signal and the at least one orthogonal code alignment signal to the one or more decoder delay adjustment blocks.

18. A receiver in an analog code division spreading system, the receiver comprising:

a plurality of receiving paths for receiving respective analog signals, each receiving path including a respective orthogonal code-encoder to perform encoding using a respective encoder code signal;

a combiner for combining a plurality of signals outputted by the orthogonal code-encoders into a combined orthogonal code-encoded analog;

an analog-to-digital converter (ADC) for obtaining digital samples of the combined orthogonal code-encoded analog signal at a sampling point; and

a decoder for decoding the digital samples using decoder code signals, the decoder comprising a synchronizer configured to;

output at least one sampling point alignment signal to apply one or more determined first time delays to the encoder code signals, the one or more first time delays being determined to align the encoder code signals with the sampling point of the ADC;

output at least one decoder code alignment signal to apply one or more determined second time delays to the decoder code signals, the one or more second time delays being determined to align the decoder code signals with the digital samples; and

output at least one orthogonal code alignment signal to apply one or more determined third time delays to the decoder code signals and encoder code signals, the one or more third time delays being determined to maintain mutual orthogonality among the decoder code signals and to maintain mutual orthogonality among the encoder code signals.

19. The receiver of claim 18, further comprising:

a known analog signal source for providing a known analog signal; and

a plurality of multiplexers, each multiplexer corresponding to a respective one receiving path, each multiplexer being configured to selectively provide the known analog signal or the respective received analog signal to the respective encoder on the receiving path.

20. The receiver of claim 18, further comprising:

a plurality of switches, each switch corresponding to a respective transmission path for transmitting a respective encoder code signal to a respective encoder, each switch being configured to selectively enable or disable transmission of the respective encoder code signal to the respective encoder.