SM4 acceleration processors, methods, systems, and instructions
First Claim
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1. A system comprising:
- a system memory; and
a processor coupled to the system memory, the processor comprising;
a data cache;
a data TLB coupled to the data cache;
a branch prediction unit;
an instruction cache;
an instruction translation lookaside buffer (TLB) coupled to the instruction cache;
an instruction fetch unit to fetch instructions, including an instruction;
a level 2 (L2) cache coupled to the data cache, and coupled to the instruction cache;
a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four round keys corresponding to four prior key expansion rounds of an SM4 cryptographic algorithm, the second register to store a second source data that includes four key generation constants;
a decode unit to decode the instruction, the instruction having a first field to specify the first register, a second field to specify the second register, and a third field to specify a destination register of the plurality of registers; and
an execution unit coupled to the decode unit, and coupled to the plurality of registers, the execution unit, in response to the decode of the instruction, to generate and store a result in the destination register, the result to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds, wherein the execution unit is to generate each of the four round keys to be consistent with an evaluation of a key expansion linear substitution function with a value for the corresponding key expansion round, which is equal to the value logically XOR'"'"'d with the value rotated left by thirteen bits logically XOR'"'"'d with the value rotated left by twenty-three bits.
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Abstract
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.
29 Citations
32 Claims
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1. A system comprising:
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a system memory; and a processor coupled to the system memory, the processor comprising; a data cache; a data TLB coupled to the data cache; a branch prediction unit; an instruction cache; an instruction translation lookaside buffer (TLB) coupled to the instruction cache; an instruction fetch unit to fetch instructions, including an instruction; a level 2 (L2) cache coupled to the data cache, and coupled to the instruction cache; a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four round keys corresponding to four prior key expansion rounds of an SM4 cryptographic algorithm, the second register to store a second source data that includes four key generation constants; a decode unit to decode the instruction, the instruction having a first field to specify the first register, a second field to specify the second register, and a third field to specify a destination register of the plurality of registers; and an execution unit coupled to the decode unit, and coupled to the plurality of registers, the execution unit, in response to the decode of the instruction, to generate and store a result in the destination register, the result to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds, wherein the execution unit is to generate each of the four round keys to be consistent with an evaluation of a key expansion linear substitution function with a value for the corresponding key expansion round, which is equal to the value logically XOR'"'"'d with the value rotated left by thirteen bits logically XOR'"'"'d with the value rotated left by twenty-three bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system comprising:
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a system memory; and a processor coupled to the system memory, the processor comprising; a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four round keys corresponding to four prior key expansion rounds of an SM4 cryptographic algorithm, the second register to store a second source data that includes four key generation constants; a decode unit to decode an instruction, the instruction having a first field to specify the first register, a second field to specify the second register, and a third field to specify a destination register of the plurality of registers; and an execution unit coupled to the decode unit, and coupled to the plurality of registers, the execution unit, in response to the decode of the instruction, to generate and store a result in the destination register, the result to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds, wherein the execution unit is to generate each of the four round keys to be consistent with an evaluation of a key expansion linear substitution function with a value for the corresponding key expansion round, which is equal to the value logically XOR'"'"'d with the value rotated left by thirteen bits logically XOR'"'"'d with the value rotated left by twenty-three bits. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method comprising:
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storing data in a system memory; dynamically allocating a plurality of registers that are used to store single instruction, multiple data (SIMD) data using register renaming; receiving a first source data including four round keys corresponding to four prior key expansion rounds of an SM4 cryptographic algorithm, from a first register of the plurality of registers; receiving a second source data including four key generation constants from a second register of the plurality of registers; decoding an instruction having a first field specifying the first register, a second field specifying the second register, and a third field specifying a destination register of the plurality of registers; generating a result, in response to the decode of the instruction, the result including four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds, wherein each of the four round keys is generated to be consistent with an evaluation of a key expansion linear substitution function with a value for the corresponding key expansion round, which is equal to the value logically XOR'"'"'d with the value rotated left by thirteen bits logically XOR'"'"'d with the value rotated left by twenty-three bits; and storing the result in the destination register in response to the decode of the instruction. - View Dependent Claims (30)
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31. An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing instructions, wherein the instructions, if executed by a machine, are to cause the machine to perform operations comprising to:
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store data in a system memory; receive a first source data from a first register of a plurality of registers that are used to store single instruction, multiple data (SIMD) data, the first source data to include four round keys corresponding to four prior key expansion rounds of an SM4 cryptographic algorithm; receive a second source data including four key generation constants from a second register of the plurality of registers; generate a result that is to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds, wherein each of the four round keys is generated to be consistent with an evaluation of a key expansion linear substitution function with a value for the corresponding key expansion round, which is equal to the value logically XOR'"'"'d with the value rotated left by thirteen bits logically XOR'"'"'d with the value rotated left by twenty-three bits; and store the result in a destination register of the plurality of registers. - View Dependent Claims (32)
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Specification