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SM4 acceleration processors, methods, systems, and instructions

  • US 10,469,249 B2
  • Filed: 09/29/2018
  • Issued: 11/05/2019
  • Est. Priority Date: 07/22/2014
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a system memory; and

    a processor coupled to the system memory, the processor comprising;

    a data cache;

    a data TLB coupled to the data cache;

    a branch prediction unit;

    an instruction cache;

    an instruction translation lookaside buffer (TLB) coupled to the instruction cache;

    an instruction fetch unit to fetch instructions, including an instruction;

    a level 2 (L2) cache coupled to the data cache, and coupled to the instruction cache;

    a plurality of registers to store single instruction, multiple data (SIMD) data, including a first register, and a second register, the first register to store a first source data that includes four round keys corresponding to four prior key expansion rounds of an SM4 cryptographic algorithm, the second register to store a second source data that includes four key generation constants;

    a decode unit to decode the instruction, the instruction having a first field to specify the first register, a second field to specify the second register, and a third field to specify a destination register of the plurality of registers; and

    an execution unit coupled to the decode unit, and coupled to the plurality of registers, the execution unit, in response to the decode of the instruction, to generate and store a result in the destination register, the result to include four round keys corresponding to four sequential key expansion rounds of the SM4 cryptographic algorithm that sequentially follow the four prior key expansion rounds, wherein the execution unit is to generate each of the four round keys to be consistent with an evaluation of a key expansion linear substitution function with a value for the corresponding key expansion round, which is equal to the value logically XOR'"'"'d with the value rotated left by thirteen bits logically XOR'"'"'d with the value rotated left by twenty-three bits.

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