Regularized parameter adaptation

• US 10,469,290 B1
• Filed: 11/01/2017
• Issued: 11/05/2019
• Est. Priority Date: 06/20/2017
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Marrow, Marcus, Bellorado, Jason
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US15/800,738
• Time in Patent Office: 734 Days
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10055 using partial response filtering when writing the signal to the medium or reading it therefrom
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403
• CPC Class Codes: G11B 20/1024 wherein a phase-locked loop [PLL] is used
• CPC Class Codes: G11B 5/59633 Servo formatting G11B5/59627, G11B5/59677, G11B5/59683, G11B5/59688 take precedence
• CPC Class Codes: G11B 5/59666 Self servo writing
• CPC Class Codes: H03G 3/20 Automatic control H03G3/005 takes precedence; combined with volume compression or expansion H03G7/00
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03M 1/001 Analogue/digital/analogue conversion
• CPC Class Codes: H03M 1/12 : Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 13/2951 : using iteration stopping criteria
• CPC Class Codes: H03M 13/4146 : soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
• CPC Class Codes: H04B 1/71055 : using minimum mean squared error [MMSE] detector
• CPC Class Codes: H04L 25/03019 : adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 7/0025 : interpolation of clock signal
• CPC Class Codes: H04L 7/0029 : interpolation of received data signal
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

An apparatus may include a circuit configured to process at least one input signal using a set of channel parameters. The circuit may adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters. The circuit may then perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.

Claims

1. An apparatus comprising:

a circuit configured to process at least one input signal using a set of channel parameters, the circuit further configured to;

adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters, the regularized adaptation algorithm further including an adjustable parameter that scales the penalty for deviation by the first set of channel parameters from the second set of channel parameters; and

perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.

2. The apparatus of claim 1, further comprising the circuit further including a Multiple-Input Single Output (MISO) equalizer that performs the processing of the at least one input signal using the set of channel parameters as filter taps.

3. The apparatus of claim 2, further comprising the at least one input signal being a plurality of digital signals that correspond to a plurality of read heads.

4. The apparatus of claim 3, further comprising the second set of channel parameters being generated using an unregularized version of the regularized adaptation algorithm during a prior on-track read.

5. The apparatus of claim 3, further comprising:

a memory storing the second set of channel parameters;

the at least one input signal based on readback signals read by the plurality of read heads from a sector of a magnetic storage medium; and

the second set of channel parameters corresponding to an area of the magnetic storage medium including the sector.

6. The apparatus of claim 3, the circuit further comprising

a plurality of analog to digital converters (ADCs), each of the plurality of digital signals being generated by a corresponding ADC of the plurality of ADCs;

the MISO equalizer comprising;

a plurality of finite impulse response (FIR) filters, the set of channel parameters including filter taps of the plurality of finite impulse response filters, each of the plurality of digital signals being processed by a corresponding FIR filter of the plurality of finite impulse response filters; and

a combiner circuit that combines the outputs of the plurality of FIR filters.

7. The apparatus of claim 6, further comprising the circuit further including a detector that performs bit detection operations on the output of the MISO equalizer, the circuit further configured to:

determine a target based on detector decisions of the detector and a channel impulse response;

determine an error based on a difference of the MISO equalizer output and the target; and

perform the adaptation based on the error.

8. The apparatus of claim 1 further comprising the regularized adaptation algorithm being a regularized least mean squares (LMS) adaptation algorithm or a regularized minimum mean squared error (MMSE) adaptation algorithm.

9. A system comprising:

a channel circuit including a Multiple-Input Single Output (MISO) equalizer and configured to process at least one input signal using a set of channel parameters being filter taps of the MISO equalizer;

an adaptation circuit configured to;

adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the channel circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a predetermined corresponding second set of channel parameters, the regularized adaptation algorithm being a regularized least mean squares (LMS) adaptation algorithm or a regularized minimum mean squared error (MMSE) adaptation algorithm, and the regularized adaptation algorithm including an adjustable parameter that scales the penalty for deviation by the first set of channel parameters from the second set of channel parameters.

10. The system of claim 9 further comprising the at least one input signal being a plurality of digital signals that correspond to a plurality of read heads.

11. The system of claim 10 further comprising:

a memory storing the second set of channel parameters, the second set of channel parameters being generated using an unregularized version of the regularized adaptation algorithm during a prior on-track read;

the at least one input signal based on readback signals read by the plurality of read heads from a sector of a magnetic storage medium; and

the second set of channel parameters corresponding to an area of the magnetic storage medium including the sector.

12. The system of claim 9 further comprising:

a plurality of analog to digital converters (ADCs), each of the plurality of digital signals being generated by a corresponding ADC of the plurality of ADCs;

the MISO equalizer comprising;

a plurality of finite impulse response (FIR) filters, the set of channel parameters including filter taps of the plurality of finite impulse response filters, each of the plurality of digital signals being processed by a corresponding FIR filter of the plurality of FIR filters; and

a combiner circuit that combines the outputs of the plurality of FIR filters;

a detector that performs bit detection operations on the output of the MISO equalizer;

a target circuit configured to;

determine a target based on detector decisions of the detector and a channel impulse response;

determine an error based on a difference of the MISO equalizer output and the target; and

the adaptation circuit further configured to perform the adaptation based on the error.

13. A method comprising:

adapting, by a circuit configured to process at least one input signal using a set of channel parameters and using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters, the regularized adaptation algorithm further including an adjustable parameter that scales a penalty for deviation by the first set of channel parameters from the second set of channel parameters; and

performing the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.

14. The method of claim 13 further comprising the circuit including a Multiple-Input Single Output (MISO) equalizer that uses the set of channel parameters as filter taps to perform the processing of the at least one input signal.

15. The method of claim 14 further comprising the regularized adaptation algorithm being a regularized least mean squares (LMS) adaptation algorithm or a regularized minimum mean squared error (MMSE) adaptation algorithm.

16. The method of claim 13 further comprising:

the at least one input signal being one or more digitized sample sequences corresponding to a sector of a magnetic storage medium;

the second set of channel parameters corresponding to an area of the magnetic storage medium including the sector and being generated using an unregularized version of the regularized adaptation algorithm during a prior on-track read of data written to the area of the magnetic storage medium including the sector.