Reconfigurable multiplexer

• US 10,469,316 B2
• Filed: 12/01/2016
• Issued: 11/05/2019
• Est. Priority Date: 12/04/2015
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Hou, Yang, Kasnavi, Reza, Ni, Jianxing, Zhao, Shanshan
• Primary Examiner(s): Skripnikov, Alex
• Assistant Examiner(s): Chowdhury, Sharmin
• Application Number:
  US15/366,326
• Publication Number:
  US 20170163297A1
• Time in Patent Office: 1,069 Days
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04B 1/0057 using diplexing or multiplexing filters for selecting the desired band
• CPC Class Codes: H04B 1/006 using switches for selecting the desired band H04B1/0057 takes precedence
• CPC Class Codes: H04L 41/0816 the condition being an adaptation, e.g. in response to network events
• CPC Class Codes: H04L 41/0823 characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability for optimising operational conditions of wireless networks H04W24/02

Abstract

A reconfigurable multiplexer that can support more frequency bands than a traditional multiplexer is disclosed. For example, the reconfigurable multiplexer can handle frequencies of several hundred megahertz up to 10 gigahertz. Further, certain implementations of the reconfigurable multiplexer can reduce or eliminate frequency dead zones that exist with traditional multiplexers. The reconfigurable multiplexer includes a filter bank capable of supporting a number of frequency bands and a bypass circuit that enables the multiplexer to support a variety of sets of frequencies. For instance, unlike traditional multiplexers, the reconfigurable multiplexer can support both frequency bands with relatively narrow spacing and frequency bands with relatively wide spacing. Further, the inclusion of the bypass circuit enables the reduction or elimination of dead zones between supported frequencies.

Claims

1. A multiplexer comprising:

a filter bank including a plurality of filters;

a bypass circuit including at least one bypass path between an input of the multiplexer and an output of the multiplexer, the at least one bypass path not including the filter bank;

a first switch that electrically connects a first filter from the plurality of filters to the output of the multiplexer based at least in part on a control signal;

a plurality of load circuits, at least a first load circuit of the plurality of load circuits configured to reduce insertion loss in a communication path between the input of the multiplexer and the output of the multiplexer, the communication path including the first filter; and

a second switch that electrically connects the at least one bypass path to the first load circuit based at least in part on the control signal being associated with a first carrier aggregation mode, and connect the at least one bypass path to the output of the multiplexer based at least in part on the control signal being associated with a non-carrier aggregation mode.

2. The multiplexer of claim 1 wherein a third switch is configured to electrically connect a second filter from the plurality of filters to a second load circuit from the plurality of load circuits based at least in part on the control signal.

3. The multiplexer of claim 2 wherein at least two load circuits from the plurality of load circuits are selectable by the third switch to be electrically connected to the second filter and the second load circuit is selected from the at least two load circuits based at least in part on the control signal.

4. The multiplexer of claim 1 wherein at least two load circuits from the plurality of load circuits are selectable by the second switch to be electrically connected to the at least one bypass path and the first load circuit is selected from the at least two load circuits based at least in part on the control signal.

5. The multiplexer of claim 1 wherein at least one load circuit from the plurality of load circuits includes a circuit having at least one inductor and at least one capacitor.

6. The multiplexer of claim 1 wherein the first switch is configured to electrically connect the first filter to an antenna based at least in part on the control signal.

7. The multiplexer of claim 1 wherein the second switch is configured to electrically connect the at least one bypass path to an antenna based at least in part on the control signal being associated with a second carrier aggregation m ode.

8. The multiplexer of claim 7 wherein the second mode is one of the non-carrier aggregation mode or a second carrier aggregation mode that is one of a subset of carrier aggregation modes that does not include the first carrier aggregation mode.

9. The multiplexer of claim 1 wherein the plurality of filters includes at least one high pass filter, band pass filter, or low pass filter.

10. The multiplexer of claim 1 wherein the bypass circuit includes a phase shift network.

11. The multiplexer of claim 1 wherein the bypass circuit includes a transmission line.

12. The multiplexer of claim 1 wherein the first carrier mode is associated with a first frequency band and a second frequency band having a spacing between the first frequency band and the second frequency band of 150 MHz or less.

13. The multiplexer of claim 1 wherein the first carrier aggregation mode is one of a subset of carrier aggregation modes.

14. A transceiver comprising:

a power amplifier module including a plurality of power amplifiers; and

a multiplexer in communication with the power amplifier module, the multiplexer including a filter bank that includes a plurality of filters, a bypass circuit, a plurality of load circuits, a first switch, and a second switch, the bypass circuit including at least one bypass path between an input of the multiplexer and an output of the multiplexer, the at least one bypass path not including the filter bank, the first switch electrically connecting a first filter from the plurality of filters to the output of the multiplexer based at least in part on a control signal, at least a first load circuit of the plurality of load circuits configured to reduce insertion loss in a communication path between the input of the multiplexer and the output of the multiplexer, the communication path including the first filter, the second switch electrically connecting the at least one bypass path to the first load circuit based at least in part on the control signal being associated with a first carrier aggregation mode and connect the at least one bypass path to the output of the multiplexer based at least in part on the control signal being associated with a non-carrier aggregation mode.

15. The transceiver of claim 14 wherein a third switch is configured to electrically connect a second filter from the plurality of filters to a second load circuit from the plurality of load circuits based at least in part on the control signal.

16. The transceiver of claim 15 wherein the third switch selects the second load circuit to electrically connect to the second filter from at least two load circuits capable of being electrically connected to the second filter.

17. The transceiver of claim 14 wherein the second switch selects the first load circuit to electrically connect to the at least one bypass path from at least two load circuits capable of being electrically connected to the at least one bypass path.

18. The transceiver of claim 14 wherein the first carrier aggregation mode is one of a first subset of carrier aggregation modes, and the second switch electrically connects the at least one bypass path to an antenna when the control signal is associated with a second aggregation mode that is one of a second subset of carrier aggregation modes.

19. A wireless device comprising:

a transceiver including a power amplifier module and a multiplexer, the power amplifier module including a plurality of power amplifiers and the multiplexer in communication with the power amplifier module, the multiplexer including a filter bank that includes a plurality of filters, a bypass circuit, a plurality of load circuits, a first switch, and a second switch, the bypass circuit including at least one bypass path between an input of the multiplexer and an output of the multiplexer, the at least one bypass path not including the filter bank, the first switch electrically connecting a first filter from the plurality of filters to the output of the multiplexer based at least in part on a control signal, at least a first load circuit of the plurality of load circuits configured to reduce insertion loss in a communication path between the input of the multiplexer and the output of the multiplexer, the communication path including the first filter, the second switch electrically connecting the at least one bypass path to the first load circuit based at least in part on the control signal being associated with a particular subset of carrier aggregation modes and connect the at least one bypass path to the output of the multiplexer based at least in part on the control signal being associated with a non-carrier aggregation mode; and

a baseband processor configured to provide the control signal to the multiplexer, the control signal determined based at least in part on a communication from a base station.

20. The wireless device of claim 19 wherein the load circuit is configured to increase isolation of a signal received by the multiplexer.