Dynamic independent test partition clock

• US 10,473,720 B2
• Filed: 10/27/2016
• Issued: 11/12/2019
• Est. Priority Date: 10/27/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Datla Jagannadha, Pavan Kumar, Jayaraman, Dheepakkumaran, Sinha, Anubhav, Natarajan, Karthikeyan, Sarangi, Shantanu, Sanghani, Amit, Sonawane, Milind, Yilmaz, Mahmut
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US15/336,626
• Publication Number:
  US 20170115351A1
• Time in Patent Office: 1,111 Days
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

Claims

1. A chip test system comprising:

a plurality of test partitions, wherein at least one of the plurality of test partitions comprises;

a partition test interface controller configured to control testing within the at least one test partition in accordance with dynamic selection of a test mode from a plurality of test modes, wherein the dynamic selection of the test mode and control of testing within the at least one of the plurality of test partitions is independent of selection of a test mode and control in others of the plurality of test partitions; and

a test chain configured to perform test operations, the test scan test chain coupled to the partition test interface controller; and

a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins.

2. The chip test system of claim 1, wherein a free running clock signal coupled to the at least one test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

3. The chip test system of claim 1, wherein the partition test interface controller generates a local partition scan enable signal, scan shift clock signal, and scan capture clock signal.

4. The chip test system of claim 1, wherein the test operations are associated with a Joint Test Action Group (JTAG) test.

5. The chip test system of claim 1, wherein the test operations are associated with a scan test.

6. The chip test system of claim 1, wherein the test operations are associated with a Memory Built In Self Test (MBIST).

7. The test system of claim 1, wherein the test operations are associated with an Input/Output Built In Self Test (IOBIST).

8. The test system of claim 1, wherein the partition test interface controller comprises a finite state machine and a clock gate.

9. A test system comprising:

a first test partition means configured to execute a first test pattern;

a second test partition means configured to execute a second test pattern, wherein the second test partition means executes at least a portion of the second test pattern in parallel with execution of at least a portion of the first test pattern on the first test partition means, and the portion of the second test pattern and the portion of the first test pattern are associated with different test modes selected from a plurality of test modes; and

a centralized controller means configured to coordinate testing between the plurality of test partition means, wherein the coordination includes managing communication of test information between the plurality of test partitions means and external pins.

10. The test system of claim 9, wherein the second test partition means includes a test partition interface controller means coupled to a free running clock signal from a single external pin, wherein the test partition interface controller means derives a local test clock signal that is different than the free running clock signal.

11. The test system of claim 9, wherein the second test pattern is reused for a third test partition means that has a shared partition design with the second test partition means.

12. The test system of claim 9, wherein test operations associated with different test modes are aligned non-sequentially between the first test partition means and the second test partition means.