×

Dynamically controlling cache size to maximize energy efficiency

  • US 10,474,218 B2
  • Filed: 12/18/2018
  • Issued: 11/12/2019
  • Est. Priority Date: 10/31/2011
  • Status: Active Grant
First Claim
Patent Images

1. A processor comprising:

  • a plurality of cores, wherein each of the plurality of cores includes a plurality of caches;

    a shared cache coupled to the plurality of cores, wherein the shared cache is to be shared by the plurality of cores, and wherein the shared cache includes a plurality of portions that each include at least one way; and

    a power control circuitry coupled to the plurality of cores and to the shared cache, the power control circuitry to;

    determine a number of cache hits, and a number of cache misses, to the shared cache from the plurality of cores;

    provide control for a dynamically variable size of the shared cache available for use by the plurality of cores, through at least one of the plurality of portions being enabled or disabled, based at least in part on the determined numbers of cache hits and cache misses; and

    provide control for at least one of the plurality of portions of the shared cache being maintained in a retention state, when the plurality of cores are to be in a low power state, and while at least another of the plurality of portions of the shared cache is to be in a lower power state than the retention state, wherein in the retention state data stored in the at least one of the plurality of portions, which is being maintained in the retention state, is to be retained.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×