Information processing apparatus, information processing method, and computer program product

• US 10,474,494 B2
• Filed: 02/21/2017
• Issued: 11/12/2019
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanai, Jun, Takumi, Shinya, Hashimoto, Mikio, Isozaki, Hiroshi
• Primary Examiner(s): Kim, Dong U
• Application Number:
  US15/438,222
• Publication Number:
  US 20180081712A1
• Time in Patent Office: 994 Days
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An information processing apparatus according to an embodiment includes a reception unit and switching unit. The reception unit receives an interrupt. The switching unit that switches a second operating system (OS) which is executing in a core to a first OS to which the interrupt for the first OS is input, when the reception unit receives an interrupt for the core in which the first OS is a priority OS and the second OS is not the priority OS.

Claims

1. An information processing apparatus, comprising:

a processor that includes a plurality of cores, the processor configured to function as;

an inter-core interrupt generating unit that generates an interrupt in a designated core;

a virtual machine monitor (VMM); and

a plurality of operating systems (OSs),

wherein the VMM is configured to function as;

a reception unit that receives an interrupt;

a first setting unit that assigns a task to a priority operating system (OS), each of the plurality of cores having the plurality of Oss including the priority OS; and

a switching unit that switches a second OS, which is executing in a first core, to a first OS to which an interrupt for the first OS is input, when the reception unit receives an interrupt for the first core among the plurality of cores in which the first OS is the priority OS and the second OS is not the priority OS; and

each of the plurality of the OSs is configured to function as;

a second setting unit that assigns a real time task to a core among the plurality of cores, in which an OS executing the real time task is set as the priority OS, the real time task having a process priority level higher than that of a non-real time task;

a selection unit that selects the real time task when an OS executed in the first core is the priority OS and the real time task is in an executable state, and selects the non-real time task when an OS executed in the first core is the priority OS, the non-real time task is in an executable state, and the real time task is not in the executable state;

a processing unit that processes the real time task selected by the selection unit or the non-real time task selected by the selection unit; and

a communication unit that, when an inter-OS communication request for requesting for communication between OSs is received from the real time task, inputs an inter-core interrupt request, in which a core with a communication destination OS being set as the priority OS is designated, to the inter-core interrupt generating unit and, when the inter-OS communication request is received from the non-real time task, inputs an inter-core interrupt request in which a core with the communication destination OS being not set as the priority OS is designated, to the inter-core interrupt generating unit.

2. The apparatus according to claim 1,

wherein the reception unit inputs the interrupt to the first OS when the second OS is switched to the first OS or when the OS executed in the first core is the first OS at the time that the reception unit receives the interrupt, and keeps the interrupt on pending when the OS executed in the first core is the second OS differing from the first OS at the time that the reception unit receives the interrupt and the second OS is not switched to the first OS.

3. The apparatus according to claim 2,

wherein the switching unit switches the second OS to the first OS when a request for switching the second OS to the first OS is received by the reception unit from the second OS that is executing, and

the reception unit inputs the interrupt to the first OS when the interrupt input to the first OS is kept on pending.

4. The apparatus according to claim 1,

wherein the selection unit selects the non-real time task when the OS executed in the first core is not the priority OS and the non-real time task is present.

5. The apparatus according to claim 1,

wherein the reception unit receives a request for switching an OS executed in the first core when the OS executed in the first core is not the priority OS and the non-real time task is not present.

6. The apparatus according to claim 1, wherein

the processor is configured to further function as an interrupt setting unit that sets a notification destination of an interrupt, and

when the OS executed in the first core is switched to the priority OS, the interrupt setting unit performs setting such that the priority OS is notified of an interrupt input to the priority OS, and performs setting such that an interrupt input to a non-priority OS differing from the priority OS is kept pending.

7. The apparatus according to claim 6,

wherein, when the OS executed in the first core is switched to the non-priority OS, the interrupt setting unit performs setting such that an interrupt input to the non-priority OS as a switching destination OS is not kept pending and is input to the non-priority OS, and performs setting such that the interrupt input to the priority OS is input to the reception unit.

8. The apparatus according to claim 1, wherein the processor is configured to further function as a verification unit that verifies completeness of data of a verification target by calculating a first hash value of the data of the verification target of an alteration stored in the information processing apparatus and comparing the first hash value with a second hash value of the data of the verification target that is not altered.

9. The apparatus according to claim 1, wherein the processor is configured to further function as a protection unit that prohibits rewriting of data of a protection target stored in the information processing apparatus.

10. An information processing method of an information processing apparatus including a processor that includes a plurality of cores, the information processing method comprising:

generating an interrupt in a designated core among the plurality of cores,

wherein the processor is configured to function as;

a virtual machine monitor (VMM); and

a plurality of operating systems (OSs),

wherein the VMM is configured to perform the following functions;

receiving an interrupt;

assigning a priority operating system (OS) to each of the plurality of cores; and

switching a second OS which is executing in a first core, to a first OS to which an interrupt for the first OS is input, when an interrupt for the first core among the plurality of cores in which the first OS is the priority OS and the second OS is not the priority OS, is received; and

wherein each of the plurality of the OSs is configured to perform the following functions;

assigning a real time task to a core among the plurality of cores, in which an OS executing the real time task is set as the priority OS, the real time task having a process priority level higher than that of a non-real time task;

selecting the real time task when an OS executed in the first core is the priority OS and the real time task is in an executable state, and selecting the non-real time task when an OS executed in the first core is the priority OS, the non-real time task is in an executable state, and the real time task is not in the executable state;

processing the real time task or the non-real time task; and

when an inter-OS communication request for requesting for communication between OSs is received from the real time task, inputting an inter-core interrupt request, in which a core with a communication destination OS being set as the priority OS is designated, to the inter-core interrupt generating unit and, when the inter-OS communication request is received from the non-real time task, inputting an inter-core interrupt request in which a core with the communication destination OS being not set as the priority OS is designated, to the inter-core interrupt generating unit.

11. A computer program product having a non-transitory computer-readable medium that stores therein a computer program causing an information processing apparatus including a processor that includes a plurality of cores to function as:

an inter-core interrupt generating unit that generates an interrupt in a designated core;

a virtual machine monitor (VMM); and

a plurality of operating systems (OSs),

wherein the VMM is configured to function as;

a reception unit that receives an interrupt;

a first setting unit that assigns a task to a priority operating system (OS), each of the plurality of cores having the plurality of OSs including the priority OS; and

a switching unit that switches a OS, which is executing in a first core, to a first OS to which an interrupt for the first OS is input, when the reception unit receives an interrupt for the first core among the plurality of cores in which the first OS is the priority OS and the second OS is not the priority OS; and

each of the plurality of the OSs is configured to function as;

a second setting unit that assigns a real time task to a core among the plurality of cores, in which an OS executing the real time task is set as the priority OS, the real time task having a process priority level higher than that of a non-real time task;

a selection unit that selects the real time task when an OS executed in the first core is the priority OS and the real time task is in an executable state, and selects the non-real time task when an OS executed in the first core is the priority OS, the non-real time task is in an executable state, and the real time task is not in the executable state;

a processing unit that processes the real time task selected by the selection unit or the non-real time task selected by the selection unit; and

a communication unit that, when an inter-OS communication request for requesting for communication between OSs is received from the real time task, inputs an inter-core interrupt request, in which a core with a communication destination OS being set as the priority OS is designated, to the inter-core interrupt generating unit and, when the inter-OS communication request is received from the non-real time task, inputs an inter-core interrupt request in which a core with the communication destination OS being not set as the priority OS is designated, to the inter-core interrupt generating unit.