Nonvolatile memory system and a method of operating the nonvolatile memory system

• US 10,474,585 B2
• Filed: 06/01/2015
• Issued: 11/12/2019
• Est. Priority Date: 06/02/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Young-min
• Primary Examiner(s): Thammavong, Prasith
• Application Number:
  US14/727,079
• Publication Number:
  US 20150347314A1
• Time in Patent Office: 1,625 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures

Abstract

A nonvolatile memory system includes: a nonvolatile memory device that includes a nonvolatile memory cell array and a page buffer; and a memory controller that loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, and in response to a logical address received from outside the memory controller, translates the logical address into a physical address based on the mapping data that is loaded into the page buffer.

Claims

1. A nonvolatile memory system, comprising:

a nonvolatile memory device that comprises a nonvolatile memory cell array and a page buffer internally connected to bit lines of the nonvolatile memory cell array, wherein the page buffer is disposed inside the nonvolatile memory device and the page buffer buffers data while the data is programmed into the memory cell array or while the data is read from the memory cell array; and

a memory controller that transmits a first command to the nonvolatile memory device such that the nonvolatile memory device loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, receives a logical address from outside the memory controller after the mapping data is loaded into the page buffer, and transmits a second command to the nonvolatile memory device if it is determined that the mapping data includes mapping information for the logical address,

wherein the page buffer of the nonvolatile memory device transmits the mapping data to the memory controller in response to the second command, and the memory controller translates the logical address into a physical address based on the mapping data that is received from the page buffer.

2. The nonvolatile memory system of claim 1, wherein when the memory controller comprises a storage unit, the memory controller stores part of the mapping data that is stored in the nonvolatile memory cell array in the storage unit, and instructs the nonvolatile memory device to load another part of the mapping data into the page buffer.

3. The nonvolatile memory system of claim 1, wherein when the mapping data includes the mapping information corresponding to the logical address, the memory controller receives the mapping data output from the page buffer, stores the output mapping data in a storage unit that is provided in the memory controller, and performs address translation by using the mapping data stored in the storage unit.

4. The nonvolatile memory system of claim 1, wherein the page buffer comprises:

a first register that temporarily stores data that is to be programmed into the nonvolatile memory cell array or data that is to be sensed from the nonvolatile memory cell array; and

a second register that loads the mapping data from the nonvolatile memory cell array.

5. The nonvolatile memory system of claim 4, wherein the second register loads the mapping data from the nonvolatile memory cell array, or receives next data that is to be programmed into the nonvolatile memory cell array from the memory controller and temporarily stores the received next data.

6. The nonvolatile memory system of claim 1, wherein after data is read from the nonvolatile memory device or after the nonvolatile memory device enters an idle state, the memory controller instructs the nonvolatile memory device to load the mapping data into the page buffer.

7. The nonvolatile memory system of claim 1, wherein the memory controller queues first and second commands that are sequentially received from the outside of the memory controller, and during a read or write operation according to the first command, the memory controller instructs the nonvolatile memory device to load into the page buffer the mapping data comprising map information corresponding to the logical address corresponding to the second command.

8. The nonvolatile memory system of claim 1, wherein the nonvolatile memory cell array comprises a first area and a second area,

wherein the mapping data is stored in the first area and user data is stored in the second area.

9. The nonvolatile memory system of claim 8, wherein the first area comprises single-level cells that store 1-bit data per cell.

10. The nonvolatile memory system of claim 1, wherein the memory controller instructs the nonvolatile memory device to load into the page buffer part of the mapping data that is selected based on a last access time or an access frequency of the mapping data that is stored in the nonvolatile memory cell array.

11. The nonvolatile memory system of claim 1, wherein the memory controller comprises an interface unit that receives data from the outside of the memory controller or transmits data to the outside of the memory controller, wherein the interface unit performs command queuing.

12. The nonvolatile memory system of claim 1, wherein the nonvolatile memory system is applicable to a mobile electronic device.

13. A method of operating a nonvolatile memory system, the method comprising:

providing, by a memory controller, a control signal to a nonvolatile memory device;

loading, by the nonvolatile memory device, at least part of mapping data from a nonvolatile memory cell array into a page buffer in response to the control signal, wherein the page buffer buffers data while the data is programmed into the memory cell array or while the data is read from the memory cell array, the page buffer receives the at least part of the ma ping data through bit lines of the nonvolatile memory cell array, and the page buffer and the nonvolatile memory cell array are disposed inside the nonvolatile memory device;

receiving, by the memory controller, a command and a logical address from outside the memory controller;

transmitting, by the memory controller, a data output command to the nonvolatile memory device if a map hit occurs in the at least part of the mapping data loaded in the page buffer;

transmitting, by the page buffer, the at least part of the mapping data to the memory controller in response to the data output command, and

translating, by the memory controller, the logical address into a physical address based on the at least part of the mapping data that is received from in the page buffer.

14. The method of claim 13, wherein the translating of the logical address comprises:

when the mapping data includes mapping information corresponding to the logical address, the method further comprises;

outputting the mapping data from the page buffer and storing the mapping data in a storage unit of the memory controller, and

translating the logical address into the physical address by using the mapping data stored in the storage unit.

15. The method of claim 13, wherein the loading of the at least part of the mapping data into the page buffer comprises queuing a first command and a second command that are sequentially received from the outside of the memory controller, and during a read or write operation according to the first command, loading into the page buffer the mapping data comprising mapping information corresponding to the logical address corresponding to the second command.

16. A nonvolatile memory system, comprising:

a nonvolatile memory device including a memory cell array and a page buffer connected to bit lines of the memory cell array, wherein the page buffer buffers data while the data is programmed into the memory cell array or while the data is read from the memory cell array and the memory cell array is configured to store mapping data in a first time period; and

a memory controller configured to instruct the page buffer to receive the mapping data through the bit lines from the memory cell array and cache the mapping data in a second time period, determine whether a map hit occurs in the cached mapping data in response to a command and a logical address in a third time period, receive the cached mapping data from the page buffer when there is a map hit in a fourth time period, and translate the logical address into a physical address based on the received cached mapping data in a fifth time period,

wherein the first, second, third, fourth and fifth time periods occur in sequence.

17. The nonvolatile memory system of claim 16, wherein the mapping data is cached in the page buffer after a read operation or when the nonvolatile memory device is in an idle state.

18. The nonvolatile memory system of claim 16, wherein the map hit occurs when the logical address is found in the mapping data that was cached in the page buffer.

19. The nonvolatile memory system of claim 16, wherein the memory controller includes a storage unit configured to store the cached mapping data received from the page buffer.

20. The nonvolatile memory system of claim 16, wherein the memory controller includes a flash translation layer configured to translate the logical address into the physical address.