Fan-out semiconductor package

• US 10,474,868 B2
• Filed: 04/12/2018
• Issued: 11/12/2019
• Est. Priority Date: 08/22/2016
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Baek, Yong Ho, Cho, Jung Hyun, Kim, Byoung Chan
• Primary Examiner(s): Semenenko, Yuriy
• Application Number:
  US15/951,677
• Publication Number:
  US 20180232556A1
• Time in Patent Office: 579 Days
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing
• CPC Class Codes: G06V 40/1329 Protecting the fingerprint sensor against damage caused by the finger
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/24155 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/244 : Connecting portions
• CPC Class Codes: H01L 2224/25171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/25175 : Parallel arrangements
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/26 : Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.

Claims

1. A fan-out semiconductor package comprising:

first insulating layers having a through-hole penetrating through outermost surfaces of the first insulating layers opposing each other;

first redistribution layers disposed on or in the first insulating layer, respectively;

first vias disposed in the first insulating layers, respectively, and electrically connecting the first redistribution layers to each other;

a semiconductor chip disposed in the through-hole of the first insulating layers, and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant covering one of the inactive surface and the active surface of the semiconductor chip, covering one of the outermost surfaces of the first insulating layers, and extending continuously from the covered surface of the semiconductor and the covered outermost surface of the first insulating layers to fill at least a portion of the through-hole;

second insulating layers and second redistribution layers alternatively disposed on the semiconductor chip, the first insulating layers, and the first redistribution layers; and

second vias disposed in the second insulating layers, respectively, and electrically connecting the second redistribution layers to each other,

wherein the second redistribution layers are electrically connected to the connection pads,

at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint and protrudes from one of the second insulating layers, and

the one of the second insulating layers, from which the at least one of the second redistribution layers including the sensor patterns protrudes, is disposed between the semiconductor chip and the at least one of the second redistribution layers including the sensor patterns.

2. The fan-out semiconductor package of claim 1, wherein the sensor patterns include Tx patterns and Rx patterns formed on different layers, and

the Tx patterns and the Rx patterns are disposed in a mesh form.

3. The fan-out semiconductor package of claim 2, wherein a line width of the Tx patterns is greater than that of the Rx patterns, and

an interval between the Tx patterns is smaller than that between the Rx patterns.

4. The fan-out semiconductor package of claim 1, wherein the sensor patterns include Tx patterns and Rx patterns formed on the same layer, and

the Tx patterns and the Rx patterns are alternatively disposed in a diamond form.

5. The fan-out semiconductor package of claim 1, further comprising a passivation layer disposed on the second connection insulating layers,

wherein the passivation layer has a dielectric constant greater than those of the second insulating layers.

6. The fan-out semiconductor package of claim 1,

wherein at least one of the second redistribution layers includes an electromagnetic wave blocking pattern.

7. The fan-out semiconductor package of claim 1, wherein an insulating layer, most adjacent to the semiconductor chip, of the second insulating layers, has a thickness greater than those of the other of the second insulating layers.

8. The fan-out semiconductor package of claim 1,

wherein the second insulating layers and the second redistribution layers are alternately disposed on the active surface of the semiconductor chip, and

the first redistribution layers are electrically connected to the semiconductor chip at least by the second redistribution layers.

9. The fan-out semiconductor package of claim 1, further comprising third redistribution layers and third insulating layers alternately disposed on the active surface the semiconductor chip, the first insulating layers, the first redistribution layers,

wherein the third redistribution layers are electrically connected to the connection pads,

the second redistribution layers and the second insulating layers are alternately disposed on the inactive surface of the semiconductor chip, and

the second redistribution layers and the third redistribution layers are connected to each other at least by the first redistribution layers.

10. The fan-out semiconductor package of claim 1, further comprising a passive component disposed in the through-hole,

wherein the passive component is electrically connected to the connection pads.

11. The fan-out semiconductor package of claim 1, wherein one of the first redistribution layers is embedded in an outermost one among the first insulating layers.

12. The fan-out semiconductor package of claim 11, wherein a lower surface of the one of the first redistribution layers has a step with respect to a lower surface of the outermost one among the first insulating layers.

13. The fan-out semiconductor package of claim 1, wherein outermost ones of the first redistribution layers protrude on outermost ones of the first insulating layers, respectively.

14. The fan-out semiconductor package of claim 13, wherein the number of the first insulating layers is three and the number of the first redistribution is four.

15. The fan-out semiconductor package of claim 14, wherein a center one of the first insulating layers has a thickness greater than that those of the other first insulating layers.

16. The fan-out semiconductor package of claim 1, where the encapsulant extends continuously from the through-hole to a region between the semiconductor chip and an insulating layer, most adjacent to the semiconductor chip, among the second insulating layers.

17. A fan-out semiconductor package comprising:

first insulating layers having a through-hole penetrating through outermost surfaces of the first insulating layers opposing each other;

first redistribution layers alternately disposed separated by the first insulating layers;

first vias disposed in the first insulating layers, respectively, and electrically connecting the first redistribution layers to each other;

a semiconductor chip disposed in the through-hole of the first insulating layers, and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip;

second insulating layers and second redistribution layers alternately disposed on one side of the semiconductor chip, the first insulating layers, and the first redistribution layers; and

second vias disposed in the second insulating layers, respectively, and electrically connecting the second redistribution layers to each other,

wherein the second redistribution layers are electrically connected to the connection pads,

one of the second redistribution layers includes sensor patterns recognizing a fingerprint and protrudes from one of the second insulating layers, and another of second redistribution layers includes an electromagnetic wave blocking pattern disposed between the semiconductor chip and the sensor patterns, and

the one of the second insulating layers, from which the one of the second redistribution layers including the sensor patterns protrudes, is disposed between the semiconductor chip and the one of the second redistribution layers including the sensor patterns.

18. The fan-out semiconductor package of claim 17, wherein the second redistribution layers include one layer disposed between the electromagnetic wave blocking pattern and the semiconductor chip and electrically connected to the connection pads of the semiconductor chip.

19. A fan-out semiconductor package comprising:

a first insulating layer having a through-hole;

a semiconductor chip disposed in the through-hole of the first insulating layer, and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant covering one of the inactive surface and the active surface of the semiconductor chip, covering one of major surfaces of the first insulating layer, and extending continuously from the covered surface of the semiconductor chip and the covered major surface of the first insulating layer to fill at least a portion of the through-hole;

a first upper redistribution layer, a first upper insulating layer, a second upper redistribution layer, and a second upper insulating layer sequentially disposed on the semiconductor chip and the first insulating layer;

a lower redistribution layer disposed between the second upper insulating layer and the semiconductor chip; and

a lower insulating layer, from which the lower redistribution layer protrudes, disposed between the lower redistribution layer and the semiconductor chip,

wherein the first and second upper redistribution layers and the lower redistribution layer are electrically connected to the connection pads,

the first and second upper redistribution layers each include sensor patterns recognizing a fingerprint, and protrude from the first and second upper insulating layers, respectively, and

the lower insulating layer is in physical contact with the semiconductor chip.

20. The fan-out semiconductor package of claim 19, wherein the first and second upper redistribution layers, the lower redistribution layer, the first and second upper insulating layers, and the lower insulating layer are disposed on a side of the active surface of the semiconductor chip, and

the fan-out semiconductor package further comprises another lower redistribution layer including an electromagnetic wave blocking pattern disposed between the second upper redistribution layer and the lower redistribution layer.