Semiconductor substrate and manufacturing method thereof

• US 10,475,637 B2
• Filed: 05/04/2017
• Issued: 11/12/2019
• Est. Priority Date: 07/13/2016
• Status: Active Grant

• Current Assignee: GlobalWafers Co., Ltd. (Sino-American Silicon Products Incorporated)
• Original Assignee: GlobalWafers Co., Ltd. (Sino-American Silicon Products Incorporated)
• Inventors: Fan, Chun-I, Chuang, Chih-Yuan, Shih, Ying-Ru, Hsu, Wen-Ching
• Primary Examiner(s): Patel, Reema
• Application Number:
  US15/586,291
• Publication Number:
  US 20180019115A1
• Time in Patent Office: 922 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02021 Edge treatment, chamfering
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body

Abstract

A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate has an epitaxy region located at a central portion of a main plane of the semiconductor substrate, a periphery region surrounding the epitaxy region and an injured region distributed inside the periphery region.

Claims

1. A semiconductor substrate, comprising:

an epitaxy region, located at a central portion of a main plane of the semiconductor substrate;

a periphery region, surrounding the epitaxy region; and

an injured region, distributed inside the periphery region;

wherein the semiconductor substrate is a Si-substrate, an average depth of the injured region is from 17.5 μ

m to 26.5 μ

m, and the injured region is a lattice strain region, and

wherein the main plane of the semiconductor substrate is surrounded by a bevel portion which is manufactured by a deformation process, the bevel portion is located in the periphery region, and the injured region is located in the bevel portion.

2. The semiconductor substrate as recited in claim 1, wherein the injured region is located in an upper portion of the bevel portion.

3. The semiconductor substrate as recited in any one of claim 1, wherein the periphery region comprises a rough region.

4. A manufacturing method of a semiconductor substrate, comprising:

providing a semiconductor substrate; and

forming an injured region inside a periphery region of the semiconductor substrate, wherein an average depth of the injured region is from 17.5 μ

m to 26.5 μ

m and the injured region is a lattice strain region, wherein a bevel portion manufactured by a deformation process is located in the periphery region, and the injured region is located in the bevel portion, and the step of forming the injured region comprises;

performing a sandblasting process or a stealth laser process to form the injured region inside the periphery region.