Fan-out semiconductor package module

• US 10,475,776 B2
• Filed: 02/20/2018
• Issued: 11/12/2019
• Est. Priority Date: 10/27/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yeong A, Kim, Eun Sil, Ko, Young Gwan, Kuroyanagi, Akihisa, Kim, Jin Su, Myung, Jun Woo
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): Tang, Sue
• Application Number:
  US15/900,568
• Publication Number:
  US 20190131285A1
• Time in Patent Office: 630 Days
• Field of Search: 257668
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/165 : Containers
• CPC Class Codes: H01L 28/40 : Capacitors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.

Claims

1. A fan-out semiconductor package module comprising:

a core member having a first through-hole and a second through-hole spaced apart from each other;

a semiconductor chip disposed in the first through-hole, and having an active surface with a connection pad and an inactive surface opposing the active surface;

a first passive component disposed in the second through-hole;

a first encapsulant covering at least portions of the core member and the first passive component, and filling at least a portion of the second through-hole;

a reinforcing member disposed on the first encapsulant to face a first surface of the first passive component;

a second encapsulant covering at least a portion of the semiconductor chip, and filling at least a portion of the first through-hole; and

a connection member disposed on the core member, the active surface of the semiconductor chip, and a second surface of the first passive component opposite to the first surface, the connection member including a redistribution layer electrically connected to the connection pad and to electrode pads on the second surface of the first passive component.

2. The fan-out semiconductor package module of claim 1, further comprising:

a second passive component disposed in the first through-hole, the second passive component and the semiconductor chip being located side by side,

wherein the second encapsulant covers at least a portion of the second passive component, and

the second passive component is electrically connected to the redistribution layer.

3. The fan-out semiconductor package module of claim 2, wherein the second passive component has a thickness greater than that of the first passive component.

4. The fan-out semiconductor package module of claim 2, wherein the semiconductor chip, the second passive component, and the first passive component are located side by side, and are electrically connected to each other through the redistribution layer of the connection member.

5. The fan-out semiconductor package module of claim 4, wherein the connection member further includes a via connecting each of the connection pad, the second passive component, and the first passive component to the redistribution layer, and

each of the connection pad, the second passive component, and the second passive component is physically in contact with the via.

6. The fan-out semiconductor package module of claim 2, wherein the semiconductor chip includes a power management integrated circuit (PMIC), and

each of the second passive component and the first passive component includes a capacitor.

7. The fan-out semiconductor package module of claim 2, wherein the core member further includes a third through-hole, spaced apart, from the first through-hole and the second through-hole,

the third through-hole is provided with a third passive component therein,

the first encapsulant covers at least a portion of the third passive component and fills at least a portion of the third through-hole, and

the redistribution layer is electrically connected to the third passive component.

8. The fan-out semiconductor package module of claim 1, wherein the semiconductor chip has a thickness greater than that of the core member.

9. The fan-out semiconductor package module of claim 1, wherein the first through-hole passes through the first encapsulant and the reinforcing member.

10. The fan-out semiconductor package module of claim 1, wherein the second encapsulant covers at least a portion of the reinforcing member.

11. The fan-out semiconductor package module of claim 1, wherein an upper surface of the second encapsulant is located above an upper surface of the first encapsulant.

12. The fan-out semiconductor package module of claim 1, wherein the reinforcing member includes a glass fiber, an inorganic filler, and an insulating resin.

13. The fan-out semiconductor package module of claim 1, wherein at least a surface of the reinforcing member is provided with a metal pattern thereon.

14. The fan-out semiconductor package module of claim 1, further comprising:

a metal layer disposed on a wall of the second through-hole.

15. The fan-out semiconductor package module of claim 14, wherein a wall of the first through-hole is physically in contact with the second encapsulant.

16. The fan-out semiconductor package module of claim 1, wherein the core member includes a first insulating layer in contact with the connection member, a first distribution layer in contact with the connection member and embedded in the first insulating layer, and a second distribution layer in a first surface opposing a second surface in which the first distribution layer of the first insulating layer is embedded, and

the first distribution layer and the second distribution layer are electrically connected to the connection pad.

17. The fan-out semiconductor package module of claim 16, wherein the core member further includes a second insulating layer on the first insulating layer and covering the second distribution layer, and a third distribution layer on the second insulating layer, and

the third distribution layer is electrically connected to the connection pad.

18. The fan-out semiconductor package module of claim 1, wherein the core member includes a first insulating layer, as well as a first distribution layer and a second distribution layer, respectively on opposing surfaces of the first insulating layer, and

the first distribution layer and the second distribution layer are electrically connected to the connection pad.

19. The fan-out semiconductor package module of claim 18, wherein the core member further includes a second insulating layer on the first insulating layer and covering the first distribution layer, a third distribution layer on the second insulating layer, a third insulating layer on the first insulating layer and covering the second distribution layer, and a fourth distribution layer on the third insulating layer, and

the third distribution layer and the fourth distribution layer are electrically connected to the connection pad.

20. The fan-out semiconductor package module of claim 1, wherein the reinforcing member integrally extends over the first passive component.

21. The fan-out semiconductor package module of claim 1, wherein the reinforcing member has a through-hole extending over an entirety of the semiconductor chip.

22. A fan-out semiconductor package module comprising:

a core member having a first through-hole and a second through-hole spaced apart from each other;

a semiconductor chip disposed in the first through-hole, and having an active surface with a connection pad and an inactive surface opposing the active surface;

a first passive component disposed in the second through-hole;

a first encapsulant covering at least portions of the core member and the first passive component, and filling at least a portion of the second through-hole;

a reinforcing member disposed on the first encapsulant;

a second encapsulant covering at least a portion of the semiconductor chip, and filling at least a portion of the first through-hole; and

a connection member disposed on the core member, the active surface of the semiconductor chip, and the first passive component, the connection member including a redistribution layer electrically connected to the connection pad, and the first passive component,

wherein the reinforcing member has an elastic modulus greater than that of the first encapsulant.

23. A fan-out semiconductor package module comprising:

a core member having a first through-hole and a second through-hole;

a reinforcing layer over the core member, having a first through-hole over the first through-hole of the core member, and covering the second through-hole;

a first component in the first through-hole;

a second component in the second through-hole; and

an encapsulant at least covering portions of the reinforcing layer and the first component.

24. The fan-out semiconductor package module of claim 23, wherein the encapsulant includes:

a first encapsulant covering the core member, covering the second component, and in the second through-hole of the core member; and

a second encapsulant covering the reinforcing layer, covering the first component, in the first through-hole of the reinforcing layer, and in the first through-hole of the core member.

25. The fan-out semiconductor package module of claim 23, wherein:

the first component has a first height greater than that of the core member; and

the second component has a second height less than that of the core member.

26. The fan-out semiconductor package module of claim 23, wherein:

the first through-hole of the core member is spaced apart from the second through-hole of the core member; and

the core member includes a metal layer between the first through-hole of the core member and the second through-hole of the core member.

27. The fan-out semiconductor package module of claim 23, wherein the reinforcing layer has an elastic modulus greater than that of the encapsulant.

28. The fan-out semiconductor package module of claim 23, wherein the reinforcing layer integrally extends over the second component.