Method for making non-volatile memory device

• US 10,475,803 B2
• Filed: 04/06/2018
• Issued: 11/12/2019
• Est. Priority Date: 04/06/2018
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Heryanto, Anson, Toh, Eng Huat, Sun, Yongshun, Lim, Yoke Leng, Chwa, Siow Lee
• Primary Examiner(s): Bachner, Robert G
• Application Number:
  US15/947,488
• Publication Number:
  US 20190312046A1
• Time in Patent Office: 585 Days
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

Claims

1. A method comprising:

forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG,

forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and

implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

2. The method according to claim 1, further comprising:

forming a dielectric layer between the CG and FG; and

forming an etching mask over the control gate prior to forming the implant mask.

3. The method according to claim 1, wherein the vertical oxide comprises an inter-poly oxide.

4. The method according to claim 1, comprising:

implanting lightly doped drain (LDD) and n-type dopants in the S/D regions.

5. The method according to claim 1, wherein the memory cells comprise split-gate non-volatile memory (NVM) cells.

6. The method according to claim 1, further comprising:

forming an interpoly dielectric (IPD) between the CG and FG.

7. The method according to claim 1, further comprising:

forming an oxide between the FG and the substrate.

8. The method according to claim 1, further comprising:

forming an oxide between the SG and the substrate.

9. A method comprising:

forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical inter-poly oxide (IPO) layer is formed between the SG and the CG and FG,

forming a dielectric layer between the CG and FG;

forming an etching mask over the control gate;

forming and patterning an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell;

implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

10. The method according to claim 9, comprising:

implanting lightly doped drain (LDD) and n-type dopants in the S/D regions.

11. The method according to claim 9, wherein the memory cells comprise split-gate non-volatile memory (NVM) cells.

12. The method according to claim 9, further comprising:

forming an interpoly dielectric (IPD) between the CG and FG.

13. The method according to claim 9, further comprising:

forming an oxide between the FG and the substrate.

14. The method according to claim 9, further comprising:

forming an oxide between the SG and the substrate.

15. A method comprising:

forming a first polysilicon gate layer over a substrate;

etching the first polysilicon gate layer to form a floating gate (FG) over the substrate;

consecutively forming a dielectric layer, an second polysilicon gate layer and hard mask (HM) and patterning to form a control gate (CG) over the FG with the dielectric formed between the FG and CG and the HIM formed over the CG;

forming an inter polysilicon oxide (IPO) on sides of the FG and CG;

forming a third polysilicon gate layer and etching to form a SG on a first side of the FG and CG;

forming an implant mask over a portion of the SG, CG and IPO; and

implanting dopants into the substrate using the implant mask to form a source drain (S/D) region.

16. The method according to claim 15, comprising:

implanting lightly doped drain (LDD) and n-type dopants in the S/D region.

17. The method according to claim 15, wherein the memory cells comprise split-gate non-volatile memory (NVM) cells.

18. The method according to claim 15, further comprising:

forming a tunnel oxide layer over the substrate prior to forming the first polysilicon gate layer.

19. The method according to claim 15, wherein the dielectric layer comprises an inter polysilicon dielectric (IPD).

20. The method according to claim 15, further comprising:

forming sidewall spacers over the S/D region.