Three-dimensional vertical NOR flash thin-film transistor strings
First Claim
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1. A memory structure, comprising:
- a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operations;
first and second heavily doped regions each formed above the semiconductor substrate and each extending along a first direction orthogonal to the planar surface of semiconductor substrate;
first and second lightly doped regions spaced apart from each other and each being adjacent both the first and second heavily doped regions;
first, second and third word line conductors that are electrically isolated from each other, wherein (i) each word line conductor extends lengthwise along a second direction substantially parallel to the planar surface, (ii) the first and the second word line conductors are (a) a predetermined distance apart along a third direction substantially orthogonal to both the first and second directions, and (b) provided on a first plane substantially parallel to the planar surface, and (iii) the third word line conductor is provided on a second plane that is substantially parallel to the first plane and separated a second predetermined distance from first plane; and
charge-trapping material provided between each word line conductor and each lightly doped region, forming first, second and third variable-threshold thin-film storage transistors, wherein (i) the first heavily doped region, the second heavily doped region, and the charge-trapping material provide each variable-threshold thin-film storage transistor a drain terminal, a source terminal and a charge-trapping region, respectively;
(ii) the first lightly doped region and the first word line conductor provide a channel region and a gate terminal, respectively, for the first variable-threshold thin-film storage transistor;
(iii) the second lightly doped region and the second word line conductor provide a channel region and a gate terminal, respectively, for the second variable-threshold thin-film storage transistor;
(ii) the first lightly doped region and the third word line conductor provide a channel region and a gate terminal, respectively, for the third variable-threshold thin-film storage transistor.
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Abstract
A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.
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Citations
31 Claims
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1. A memory structure, comprising:
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a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operations; first and second heavily doped regions each formed above the semiconductor substrate and each extending along a first direction orthogonal to the planar surface of semiconductor substrate; first and second lightly doped regions spaced apart from each other and each being adjacent both the first and second heavily doped regions; first, second and third word line conductors that are electrically isolated from each other, wherein (i) each word line conductor extends lengthwise along a second direction substantially parallel to the planar surface, (ii) the first and the second word line conductors are (a) a predetermined distance apart along a third direction substantially orthogonal to both the first and second directions, and (b) provided on a first plane substantially parallel to the planar surface, and (iii) the third word line conductor is provided on a second plane that is substantially parallel to the first plane and separated a second predetermined distance from first plane; and charge-trapping material provided between each word line conductor and each lightly doped region, forming first, second and third variable-threshold thin-film storage transistors, wherein (i) the first heavily doped region, the second heavily doped region, and the charge-trapping material provide each variable-threshold thin-film storage transistor a drain terminal, a source terminal and a charge-trapping region, respectively;
(ii) the first lightly doped region and the first word line conductor provide a channel region and a gate terminal, respectively, for the first variable-threshold thin-film storage transistor;
(iii) the second lightly doped region and the second word line conductor provide a channel region and a gate terminal, respectively, for the second variable-threshold thin-film storage transistor;
(ii) the first lightly doped region and the third word line conductor provide a channel region and a gate terminal, respectively, for the third variable-threshold thin-film storage transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification