Three dimension integrated circuits employing thin film transistors

• US 10,475,815 B2
• Filed: 12/22/2017
• Issued: 11/12/2019
• Est. Priority Date: 09/09/2013
• Status: Active Grant

• Current Assignee: Tacho Holdings, LLC
• Original Assignee: Tacho Holdings, LLC
• Inventors: Lupino, James John, Agan, Tommy Allen
• Primary Examiner(s): Armand, Marc Anthony
• Application Number:
  US15/853,518
• Publication Number:
  US 20180122825A1
• Time in Patent Office: 690 Days
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/165 Auxiliary circuits
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H10B 61/10 : comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/20 : comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 : Switching materials
• CPC Class Codes: H10N 70/8825 : Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve the density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semi-conductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

Claims

1. An integrated circuit device comprising:

a substrate;

core circuitry manufactured on the substrate, the core circuitry comprising a plurality of electrically-interconnected crystalline transistors; and

Input/Output (I/O) circuitry located directly above and electrically coupled to the core circuitry via electrical interconnects therebetween, the I/O circuitry comprising a plurality of Thin Film Transistors (TFTs) and configured to receive and/or provide electrical signal(s) from and/or to one or more devices conductively coupled to and external to the integrated circuit device, respectively,

wherein the plurality of TFTs consists of structures manufacturable at temperatures less than or equal to 450°

C.

2. The integrated circuit of claim 1, wherein the plurality of electrically-interconnected crystalline transistors comprises Complementary Metal Oxide Semiconductor (CMOS) transistors.

3. The integrated circuit of claim 1, wherein the plurality of TFTs comprises Amorphous Oxide Semiconductor (AOS) TFTs.

4. The integrated circuit of claim 3, wherein the AOS TFTs comprise Zinc Tin Oxide (ZTO) TFTs and/or Indium-Gallium-Zinc-Oxide (IGZO) TFTs.

5. The integrated circuit of claim 1, wherein the plurality of TFTs comprise column III-Nitride (III-N) TFTs.

6. The integrated circuit of claim 1, wherein the plurality of TFTs comprise column III-Arsenic (III-As) TFTs.

7. The integrated circuit of claim 1, wherein the plurality of TFTs comprise graphene and/or carbon nanotubes.

8. The integrated circuit of claim 1, wherein the substrate is a first substrate, the integrated circuit further comprising:

a second substrate located directly above the I/O circuitry.

9. The integrated circuit of claim 8, wherein the second substrate comprises a power plane, whereby thermal energy generated by the integrated circuit is conducted via the power plane.

10. The integrated circuit of claim 8, wherein the second substrate comprises a printed circuit board.

11. The integrated circuit of claim 8, wherein the second substrate is a glass substrate.

12. The integrated circuit of claim 8, further comprising a memory array located between the I/O circuitry and the second substrate.

13. The integrated circuit of claim 12 wherein at least one of the plurality of TFTs is configured to facilitate electrical communication between the memory array and the core circuitry.

14. The integrated circuit of claim 1, wherein the core substrate is a Silicon (Si) substrate.

15. The integrated circuit of claim 1, wherein the core circuitry comprises a microprocessor (μ

P), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), and/or an Application Specific Standard Product (ASSP).

16. The integrated circuit of claim 1, wherein the core circuitry comprises memory.

17. The integrated circuit of claim 16, wherein the memory comprises SiOx memresistor cells.