Method and apparatus for image sensor packaging

• US 10,475,843 B2
• Filed: 05/09/2016
• Issued: 11/12/2019
• Est. Priority Date: 02/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Szu-Ying, Wan, Meng-Hsun, Yaung, Dun-Nian, Chen, Pao-Tung, Liu, Jen-Cheng
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): Crite, Antonio B
• Application Number:
  US15/150,187
• Publication Number:
  US 20160254306A1
• Time in Patent Office: 1,282 Days
• Field of Search: 257233, 257288, 257292, 257293, 257414, 257E21006, 257E21051, 257E21053, 257E2117, 257E2121, 257E21189, 257E21305, 257E21352, 257E21366, 257E21304, 250206, 250216
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/381 Pitch distance
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.

Claims

1. A device comprising:

a sensor die comprising;

a first substrate;

a sensor region in the first substrate;

a plurality of pixels disposed within the sensor region, each pixel of the plurality of pixels including a photodiode and a pixel control circuit formed in the first substrate; and

a plurality of sensor bond pads disposed on a first side of the first substrate and outside the sensor region, respective sensor bond pads receiving signal outputs from at least one respective pixel control circuit, at least one of the plurality of sensor bond pads being exposed at the first side of the first substrate, wherein the plurality of sensor bond pads comprises four bond pad groups, with each of the four bond pad groups extending along a respective side of the sensor region, wherein each of the four bond pad groups comprises first bond pads disposed along a first line and second bond pads disposed along a second line, wherein the first line is parallel to the second line and parallel to the respective side of the sensor region, wherein each of the first bond pads has a same offset with a respective one of the second bond pads, wherein no electrically conductive feature of the sensor die is disposed within a first area of the first side of the first substrate, the first area being directly over the sensor region; and

a control circuit die comprising;

a second substrate; and

a plurality of control circuit bond pads on a first side of the second substrate facing the first substrate, respective ones of the control circuit bond pads being bonded to respective ones of the plurality of sensor bond pads.

2. The device of claim 1, wherein transistors of the pixels are comprised solely of NMOS transistors or solely of PMOS transistors.

3. The device of claim 1, wherein the sensor die further comprises one or more redistribution layers (RDLs), the sensor bond pads disposed in an uppermost dielectric layer of the RDLs.

4. The device of claim 1, wherein the sensor bond pads have a pitch that is about 1, about 2 or about 3 times the pitch of the plurality of pixels.

5. The device of claim 1, further comprising a through via extending from a front side of the sensor die to a back side of the sensor die and electrically connecting the control circuit die to a connector on the back side of the sensor die.

6. The device of claim 1, wherein the plurality of control circuit bond pads are formed on a back side of the control circuit die and further comprising control circuit transistors formed at a front side of the control circuit die.

7. The device of claim 1, further comprising:

a plurality of row select lines, each of the plurality of row select lines extending between and electrically connected to a plurality of pixels in a row and further electrically connected to a sensor bond pad; and

a plurality of output lines, each of the plurality of output lines extending between and electrically connected to a plurality of pixels in a column and further electrically connected to a sensor bond pad.

8. The device of claim 1, wherein the same offset is measured along a direction parallel to the first line.

9. The device of claim 1, wherein the control circuit die comprises at least a vertical access circuit.

10. The device of claim 9, wherein the vertical access circuit is configured to output a pre-determined voltage to at least one of the plurality of control circuit bond pads.

11. A device comprising:

an integrated circuit die including;

a sensor region formed in a sensor substrate;

a plurality of backside illuminated pixels disposed within the sensor region;

a plurality of sensor bond pads disposed outside the sensor region and on a front side of the sensor substrate, wherein the sensor region has four sides, the plurality of sensor bond pads comprises four sensor bond pad groups, wherein each of the four sensor bond pad groups extends along a respective side of the sensor region, wherein a first sensor bond pad group of the four sensor bond pad groups extends along a first side of the sensor region, the first sensor bond pad group comprising a first plurality of sensor bond pads disposed along a first line and a second plurality of sensor bond pads disposed along a second line different from the first line, the first line and the second line being parallel to the first side of the sensor region, each of the first plurality of sensor bond pads having a same offset with a respective one of the second plurality of sensor bond pads;

a row select line electrically connected to a plurality of pixels in a row, the row select line extending from within the sensor region to outside of the sensor region and being electrically connected to a first sensor bond pad; and

an output line electrically connected to a plurality of pixels in a column, the output line extending from within the sensor region to outside of the sensor region and being electrically connected to a second sensor bond pad.

12. The device of claim 11, wherein transistors of the backside illuminated pixels are comprised solely of NMOS transistors or solely of PMOS transistors.

13. The device of claim 11, wherein transistors disposed on the sensor substrate are comprised solely of NMOS transistors or solely of PMOS transistors.

14. The device of claim 11, wherein the backside illuminated pixels comprise charge coupled devices, n-type metal oxide semiconductor devices or p-type metal oxide semiconductor devices.

15. The device of claim 11, wherein each of the plurality of pixels comprises a reset transistor having a gate, at least one sensor bond pad electrically connected to a gate of a reset transistor of at least one of the plurality of pixels.

16. The device of claim 11, further comprising a control circuit die having a first control circuit bond pad bonded to the first sensor bond pad and having a second control circuit bond pad bonded to the second sensor bond pad.

17. The device of claim 16, further comprising an electrically conductive via passing through the sensor substrate and electrically connecting a control circuit on the control circuit die to a connector on a backside of the sensor substrate.

18. A device, comprising:

a sensor die including;

a sensor array within a sensor region;

first bond pads on a topmost surface of the sensor die, the first bond pads being connected to respective outputs of respective pixels of the sensor array, the first bond pads further being configured in a pattern outside the sensor region, an area of the topmost surface of the sensor die directly over the sensor region being free of bond pads, wherein the first bond pads comprise four bond pad groups, wherein each of the four bond pad groups extends along a respective side of the sensor region and comprises;

a first plurality of bond pads disposed along a first line parallel to the respective side of the sensor region; and

a second plurality of bond pads disposed along a second line parallel to the first line, the second line being different from the first line, wherein each of the second plurality of bond pads has a same offset with a respective one of the first plurality of bond pads; and

an electrical connection structure electrically connecting respective pixels within the sensor array to respective first bond pads; and

a control circuit die mounted to the sensor die and including;

a control circuit;

second bond pads on a bottommost surface of the control circuit die, respective ones of the second bond pads being aligned with respective ones of the first bond pads; and

a second electrical connection structure electrically connecting respective nodes of the control circuit to respective second bond pads.

19. The device of claim 18, further comprising a conductive through via passing through the sensor die and electrically connecting the control circuit die to a connector on a first side of the sensor die opposite a second side of the sensor die upon which the control circuit die is mounted.

20. The device of claim 18, further comprising a redistribution layer (RDL) on the sensor die, the first bond pads disposed in an uppermost dielectric layer of the RDLs.