Display device with light blocking layer and manufacturing method thereof
First Claim
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1. A display device, comprising:
- a light blocking layer on a first substrate;
a buffer layer on the light blocking layer;
a semiconductor layer on the buffer layer;
a dummy metal layer on and directly contacting the semiconductor layer, the dummy metal layer including an opening exposing an entirety of a channel region of the semiconductor layer;
an insulating layer on the semiconductor layer in the opening and not directly contacting the dummy metal layer;
a source/drain metal layer on the insulating layer, the source/drain metal layer comprising a non-overlap region that does not overlap the light blocking layer, and overlaps the semiconductor layer; and
a gate metal layer on the insulating layer,wherein no portion of the dummy metal layer overlaps the gate metal layer in any part of the channel region of the semiconductor layer.
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Abstract
Provided are a display device and a method of manufacturing the same. A display device includes: a light blocking layer on a first substrate, a buffer layer on the light blocking layer, a semiconductor layer on the buffer layer, an insulating layer on the semiconductor layer, and a source/drain metal layer positioned on the insulating layer, the source/drain metal layer including a non-overlap region that does not overlap the light blocking layer.
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Citations
12 Claims
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1. A display device, comprising:
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a light blocking layer on a first substrate; a buffer layer on the light blocking layer; a semiconductor layer on the buffer layer; a dummy metal layer on and directly contacting the semiconductor layer, the dummy metal layer including an opening exposing an entirety of a channel region of the semiconductor layer; an insulating layer on the semiconductor layer in the opening and not directly contacting the dummy metal layer; a source/drain metal layer on the insulating layer, the source/drain metal layer comprising a non-overlap region that does not overlap the light blocking layer, and overlaps the semiconductor layer; and a gate metal layer on the insulating layer, wherein no portion of the dummy metal layer overlaps the gate metal layer in any part of the channel region of the semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification