Multi-terminal inductor for integrated circuit

• US 10,475,877 B1
• Filed: 08/21/2018
• Issued: 11/12/2019
• Est. Priority Date: 08/21/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Ching-Chung, Chang, Chung-Long, Yang, Tsung-Yu, Li, Hung-Chi, Hsieh, Cheng-Chieh, Lin, Che-Yung, Chang, Grace
• Primary Examiner(s): Dulka, John P.
• Application Number:
  US16/106,525
• Time in Patent Office: 448 Days
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 27/24 Magnetic cores
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/29 Terminals; Tapping arrangements for signal inductances
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0612 Layout
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/1412 Layout
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/1003 : Non-printed inductor

Abstract

A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

Claims

1. A multi-terminal inductor, comprising:

a semiconductor substrate;

an interconnect structure having a plurality of metal layers disposed over the semiconductor substrate;

a first magnetic layer disposed over an uppermost surface of the interconnect structure;

a conductive wire disposed over the first magnetic layer;

a first input/output (I/O) bond structure that branches off of the conductive wire at a first location;

a second I/O bond structure that branches off of the conductive wire at a second location, the second location being spaced apart from the first location; and

a third I/O bond structure that branches off of the conductive wire at a third location between the first location and the second location, wherein a connection between the third I/O bond structure and the first I/O bond structure has a first inductance and an alternative connection between the first I/O bond structure and the second I/O bond structure has a second inductance that is greater than the first inductance.

2. The multi-terminal inductor of claim 1, further comprising:

a first dielectric layer disposed over the conductive wire;

a second magnetic layer disposed over the first dielectric layer;

a second dielectric layer disposed over the second magnetic layer; and

wherein the conductive wire laterally extends from the first I/O bond structure to the second I/O bond structure in a substantially straight line along a first direction.

3. The multi-terminal inductor of claim 2, wherein the second location is laterally spaced in the first direction from outermost sidewalls of the first magnetic layer.

4. The multi-terminal inductor of claim 2, wherein the first I/O bond structure, the second I/O bond structure, and the third I/O bond structure each extend from the conductive wire through an uppermost surface of the second dielectric layer.

5. The multi-terminal inductor of claim 4, wherein the conductive wire has a first upper surface over the first magnetic layer that is above a second upper surface of the conductive wire.

6. The multi-terminal inductor of claim 1, wherein the conductive wire continuously extends from the first I/O bond structure to the second I/O bond structure in a helical pattern around the first magnetic layer.

7. The multi-terminal inductor of claim 1, wherein the multi-terminal inductor is one of a plurality of multi-terminal inductors arranged in an array, wherein each multi-terminal inductor is spaced apart from one another, wherein each multi-terminal inductor is arranged in the same lateral direction, and wherein each multi-terminal inductor is substantially identical to one another.

8. A multi-terminal inductor, comprising:

a semiconductor substrate;

an interconnect structure having a plurality of metal layers disposed over the semiconductor substrate;

a passivation layer disposed over an uppermost surface of the interconnect structure;

a magnetic layer disposed over the passivation layer;

a plurality of inductor units including a plurality of conductive wires, respectively, spaced apart from one another and arranged over the magnetic layer, wherein a first inductor unit of the plurality of inductor units includes a dielectric layer extending over a first conductive wire of the first inductor unit and includes a first terminal and a second terminal that extend through the dielectric layer to provide electrical connections to the first conductive wire of the first inductor unit; and

a connection structure disposed over the dielectric layer and having conductive traces electrically coupled to the first and second terminals, wherein the connection structure electrically couples some, but not all, of the plurality of inductor units in series with one another.

9. The multi-terminal inductor of claim 8, wherein the first terminal includes a first solder bump and the second terminal includes a second solder bump, and wherein the connection structure is a printed circuit board (PCB) having conductive traces coupling two or more of the plurality of inductor units in series with one another.

10. The multi-terminal inductor of claim 8, wherein the plurality of inductor units are substantially identical to one another.

11. The multi-terminal inductor of claim 8, wherein the first inductor unit further comprises:

a third terminal extending through the dielectric layer and electrically coupled to the first inductor unit, wherein a first inductance measured between the first terminal and the second terminal is greater than a second inductance measured between the first terminal and the third terminal.

12. The multi-terminal inductor of claim 8, wherein the first conductive wire continuously extends from the first terminal to the second terminal in a substantially straight line.

13. The multi-terminal inductor of claim 12, wherein the first inductor unit includes a second conductive wire that extends in parallel with the first conductive wire, and wherein a third terminal and a fourth terminal extend through the dielectric layer and are electrically coupled to the second conductive wire of the first inductor unit.

14. The multi-terminal inductor of claim 13, further comprising circuitry configured to pass a first current through the first conductive wire in a first direction and to pass a second current through the second conductive wire in a second direction opposite the first direction.

15. The multi-terminal inductor of claim 13, wherein a first inductance measured between the first terminal and the second terminal is substantially equal to a second inductance measured between the third terminal and the fourth terminal.

16. The multi-terminal inductor of claim 8, wherein the first conductive wire continuously extends from the first terminal to the second terminal in a helical structure around the magnetic layer.

17. The multi-terminal inductor of claim 16, wherein the first inductor unit further comprises:

a third terminal extending through the dielectric layer and electrically coupled to the first inductor unit, wherein the first terminal is located at a first end of the first conductive wire, the second terminal is located at a second end of the first conductive wire opposite the first end, and the third terminal is located at a first intermediate position on the helical structure between the first end and the second end.

18. The multi-terminal inductor of claim 17, wherein the first inductor unit further comprises:

a fourth terminal extending through the dielectric layer and electrically coupled to the first inductor unit, wherein the fourth terminal is located at a second intermediate position on the helical structure between the first end and the first intermediate position.

19. The multi-terminal inductor of claim 8, wherein the plurality of inductor units comprises a second inductor unit spaced apart from the first inductor unit and arranged over the magnetic layer, wherein the second inductor unit includes a second conductive wire which is co-linear with the first conductive wire.

20. A method, comprising:

forming an interconnect structure having a plurality of metal layers over a semiconductor substrate;

forming a passivation layer over an uppermost surface of the interconnect structure;

forming a first magnetic layer over the passivation layer;

forming a plurality of conductive wires spaced apart from one another over the first magnetic layer;

forming a dielectric layer over the plurality of conductive wires;

forming a plurality of solder bumps over the dielectric layer, wherein different solder bumps of the plurality of solder bumps are electrically coupled to different conductive wires; and

selectively connecting a printed circuit board (PCB) having conductive traces to some, but not all, of the plurality of solder bumps.