Semiconductor devices

• US 10,475,898 B2
• Filed: 03/28/2018
• Issued: 11/12/2019
• Est. Priority Date: 09/08/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Wonkeun, Kim, Jae-Jung, Jang, Jinkyu, Kim, Sangyong, Na, Hoonjoo, Lee, Dongsoo, Hyun, Sangjin
• Primary Examiner(s): Sullivan, Caleen O
• Application Number:
  US15/938,716
• Publication Number:
  US 20190081148A1
• Time in Patent Office: 594 Days
• Field of Search: 257328
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Claims

1. A semiconductor device, comprising:

first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from, each other; and

a first gate electrode on the first semiconductor patterns, the first gate electrode comprising;

a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns;

a barrier pattern on the first work function metal pattern; and

a first electrode pattern on the barrier pattern,

wherein the first gate electrode has a first part between adjacent ones of the first semiconductor patterns,

wherein the barrier pattern comprises a first metal nitride layer comprising silicon, and

wherein the barrier pattern and the first electrode pattern are spaced apart from the first part.

2. The semiconductor device of claim 1, wherein the first gate electrode has a second part on an uppermost one of the first semiconductor patterns,

wherein the first part comprises the first work function metal pattern, and

wherein the second part comprises the first work function metal pattern, the barrier pattern, and the first electrode pattern that are sequentially stacked.

3. The semiconductor device of claim 1, further comprising:

second semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other; and

a second gate electrode on the second semiconductor patterns, the second gate electrode comprising;

a second work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the second semiconductor patterns; and

a second electrode pattern on the second work function metal pattern,

wherein the second work function metal pattern comprises a work function less than that of the first work function metal pattern.

4. The semiconductor device of claim 3, wherein the first work function metal pattern comprises a second metal nitride layer, and

wherein the second work function metal pattern comprises a third metal nitride layer comprising silicon and/or aluminum.

5. The semiconductor device of claim 4, wherein the second work function metal pattern comprises the third metal nitride layer comprising silicon, and

wherein the second work function metal pattern comprises a silicon concentration that varies based on a distance from the substrate.

6. The semiconductor device of claim 3, wherein the second work function metal pattern comprises a second metal nitride layer comprising silicon, and

wherein the barrier pattern comprises a silicon concentration greater than that of the second work function metal pattern.

7. The semiconductor device of claim 3, wherein the second work function metal pattern comprises work function metal layers and an intermediate layer between the work function metal layers,

wherein respective ones of the work function metal layers comprise a second metal nitride layer comprising silicon, and

wherein the intermediate layer comprises a silicon layer.

8. The semiconductor device of claim 3, wherein the second gate electrode has the first part between adjacent ones of the second semiconductor patterns and a second part on an uppermost one of the second semiconductor patterns,

wherein the first part of the second gate electrode comprises the second work function metal pattern, and

wherein the second part of the second gate electrode comprises the second work function metal pattern and the second electrode pattern that are sequentially stacked.

9. The semiconductor device of claim 1, further comprising:

second semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other; and

a second gate electrode on the second semiconductor patterns, the second gate electrode comprising;

a second work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the second semiconductor patterns; and

a second electrode pattern on the second work function metal pattern,

wherein the first work function metal pattern comprises a first work function metal layer,

wherein the second work function metal pattern comprises the first work function metal layer and a second work function metal layer, and

wherein the second work function metal layer comprises a work function less than that of the first work function metal layer.

10. The semiconductor device of claim 1, wherein the barrier pattern comprises a silicon concentration ranging from 20 at % to 50 at %.

11. The semiconductor device of claim 1, wherein the first electrode pattern comprises a resistance less than that of the first work function metal pattern, and

wherein the first electrode pattern comprises aluminum, tungsten, titanium, and/or tantalum.

12. A semiconductor device, comprising a first transistor and a second transistor on a substrate, each of the first and second transistors comprising:

semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other; and

a gate electrode on the semiconductor patterns,

wherein the gate electrode of the first transistor comprises a first work function metal pattern and a first electrode pattern that are sequentially stacked on an uppermost one of the semiconductor patterns of the first transistor,

wherein the gate electrode of the second transistor comprises a second work function metal pattern, a barrier pattern, and a second electrode pattern that are sequentially stacked on an uppermost one of the semiconductor patterns of the second transistor, and

wherein the first electrode pattern covers the first work function metal pattern.

13. The semiconductor device of claim 12, wherein the barrier pattern comprises a silicon-containing metal nitride layer.

14. The semiconductor device of claim 12, wherein the first work function metal pattern comprises a silicon-containing and/or aluminum-containing first metal nitride layer, and

wherein the second work function metal pattern comprises a second metal nitride layer.

15. The semiconductor device of claim 12, wherein the first and second electrode patterns comprise aluminum, tungsten, titanium, and/or tantalum.

16. The semiconductor device of claim 12, wherein the gate electrode of the first transistor and the gate electrode of the second transistor each comprise a first part between adjacent ones of the semiconductor patterns,

wherein the first electrode pattern is spaced apart from the first part of the gate electrode of the first transistor, and

wherein the second electrode pattern and the barrier pattern are spaced apart from the first part of the gate electrode of the second transistor.

17. A semiconductor device, comprising:

first semiconductor patterns vertically stacked on a substrate;

second semiconductor patterns vertically stacked on the substrate;

a first gate electrode on the first semiconductor patterns; and

a second gate electrode on the second semiconductor patterns,

wherein the first gate electrode comprises;

a first work function metal pattern within a space between adjacent ones of the first semiconductor patterns and on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns; and

a first electrode pattern on the first work function metal pattern, and

wherein the second gate electrode comprises;

a second work function metal pattern within a space between adjacent ones of the second semiconductor patterns and on a top surface, a bottom surface, and sidewalls of respective ones of the second semiconductor patterns;

a second electrode pattern on the second work function metal pattern; and

a barrier pattern between the second work function metal pattern and the second electrode pattern,

wherein the first work function metal pattern comprises a silicon-containing first metal nitride layer,

wherein the second work function metal pattern comprises a second metal nitride layer,

wherein the barrier pattern comprises a silicon-containing third metal nitride layer, and

wherein the barrier pattern comprises a silicon concentration greater than that of the first work function metal pattern.

18. The semiconductor device of claim 17, wherein the first electrode pattern is spaced apart from the space between adjacent ones of the first semiconductor patterns by at least one of the first semiconductor patterns, and

the second electrode pattern and the barrier pattern are spaced apart from the space between adjacent ones of the second semiconductor patterns by at least one of the second semiconductor patterns.

19. The semiconductor device of claim 17, wherein the first semiconductor patterns and the first gate electrode are portions of a first transistor,

wherein the second semiconductor patterns and the second gate electrode are portions of a second transistor,

wherein the first and second transistors are PMOSFETs, and

wherein the first transistor has a threshold voltage greater than that of the second transistor.

20. The semiconductor device of claim 17, wherein the silicon concentration of the barrier pattern falls within a range from 20 at % to 50 at %.