Method of forming transistor with dual spacer

• US 10,475,903 B2
• Filed: 01/28/2019
• Issued: 11/12/2019
• Est. Priority Date: 11/17/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Chia-Ling, Chiang, Ping-Hung, Hsiung, Chang-Po, Lu, Chia-Wen, Li, Nien-Chung, Lee, Wen-Fang, Wang, Chih-Chung
• Primary Examiner(s): Galvin, III, Joseph M
• Application Number:
  US16/258,679
• Publication Number:
  US 20190157421A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Claims

1. A method of forming a transistor with dual spacers, comprising:

forming a gate dielectric layer and a gate electrode on a substrate, wherein the gate dielectric layer protrudes from the gate electrode;

forming a first dual spacer comprising a first inner spacer and a first outer spacer on the gate dielectric layer beside the gate electrode;

forming a second dual spacer comprising a second inner spacer having an L-shaped profile and a second outer spacer on the gate dielectric layer beside the first dual spacer;

removing the second outer spacer, thereby the gate dielectric layer comprising a first part and a second part, wherein the first part is right below the second inner spacer, and the second part is uncovered by the second inner spacer, wherein a thickness of the first part is larger than a thickness of the second part; and

forming a source/drain in the substrate beside the second dual spacer after the second dual spacer is formed, and then the second outer spacer is removed, wherein the second part vertically overlaps the source/drain completely.

2. The method of forming a transistor with dual spacers according to claim 1, further comprising:

forming a contact etch stop layer after the second outer spacer is removed.

3. The method of forming a transistor with dual spacers according to claim 1, further comprising:

forming a recess in the substrate before the gate dielectric layer and the gate electrode are formed on the substrate; and

forming the gate dielectric layer in the recess.

4. The method of forming a transistor with dual spacers according to claim 1, wherein the steps of forming the second dual spacer comprise:

forming a second inner spacer material and a second outer spacer material blanketly covering the gate dielectric layer, the gate electrode and the substrate; and

etching the second outer spacer material and the second inner spacer material, thereby the second dual spacer being formed.

5. The method of forming a transistor with dual spacers according to claim 4, wherein the method of forming the second inner spacer material and the second outer spacer material comprises using stress memorization technique (SMT).

6. The method of forming a transistor with dual spacers according to claim 4, wherein a part of the gate dielectric layer protruding from the gate electrode is etched while the second outer spacer material and the second inner spacer material are etched.

7. The method of forming a transistor with dual spacers according to claim 1, further comprising:

forming a metal silicide on the source/drain after the second outer spacer is removed.

8. The method of forming a transistor with dual spacers according to claim 7, wherein the first inner spacer has an L-shaped profile, and the first outer spacer is removed after the metal silicide is formed on the source/drain.

9. The method of forming a transistor with dual spacers according to claim 1, further comprising:

forming a spacer on the substrate beside the gate before the first dual spacer is formed; and

forming a lightly doped source/drain in the substrate beside the spacer.

10. The method of forming a transistor with dual spacers according to claim 1, further comprising:

forming a first gate on the substrate while a gate comprising the gate dielectric layer and the gate electrode is formed, wherein the gate is a gate of a medium voltage transistor while the first gate is a gate of a low voltage transistor, wherein the second dual spacer is only formed on the substrate beside the gate without forming on the substrate beside the first gate.