Method of producing an integrated power transistor circuit having a current-measuring cell

• US 10,475,919 B2
• Filed: 03/14/2017
• Issued: 11/12/2019
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Wutte, Britta
• Primary Examiner(s): Wall, Vincent
• Application Number:
  US15/458,459
• Publication Number:
  US 20170186863A1
• Time in Patent Office: 973 Days
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]

Abstract

A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

Claims

1. A method for producing an integrated power transistor circuit, the method comprising:

providing a semiconductor substrate comprising a cell array and a region outside the cell array;

forming a plurality of transistor cells of the cell array connected in parallel to form a power transistor, each of the transistor cells having a doped region formed in the semiconductor substrate and adjoining a first surface on a first side of the semiconductor substrate, a channel region and a gate conductor structure;

forming an electrode structure on the first side of the semiconductor substrate in a projection of the cell array orthogonal to the first surface;

forming a gate electrode on the first side of the semiconductor substrate outside the cell array, the gate electrode being physically separated from and electrically connected to each gate conductor structure, wherein each gate conductor structure extends in a longitudinal direction from the cell array into the region outside the cell array and under the gate electrode;

forming a contact structure on the first side of the semiconductor substrate and electrically conductively connected to the doped region and the electrode structure, the contact structure having a first section between the electrode structure and the semiconductor substrate above the cell array, a second section above the region outside the cell array and connecting the first section to an interface structure in the region outside the cell array, and a third section arranged on the first side of the semiconductor substrate outside the cell array and between the gate electrode and the semiconductor substrate, the third section being electrically insulated and physically separated from the first and the second sections;

forming a dielectric layer between the first surface and the contact structure in both the cell array and the region outside the cell array; and

forming plated-through holes in the cell array which extend through the dielectric layer and electrically connect the contact structure to the doped region and the channel region of each transistor cell of the power transistor,

wherein the dielectric layer has a bottom surface in the cell array and the region outside the cell array,

wherein the bottom surface is located in the same plane in both the cell array and the region outside the cell array,

wherein the first surface contacts the bottom surface of the dielectric layer.

2. The method of claim 1, further comprising:

forming the doped region of each transistor cell as a strip extending along the longitudinal direction,

wherein the second section of the contact structure has one or more first subsections, which each extend, starting from the first section, in the longitudinal direction, and a second subsection, which adjoins the one or more first subsections and extends along a different direction, which intersects the first direction.

3. The method of claim 2, further comprising:

forming the second subsection of the contact structure as a strip extending parallel to a straight edge of the electrode structure.

4. The method of claim 2, further comprising:

forming the second subsection of the contact structure as a strip extending parallel to a straight edge of the gate electrode.

5. The method of claim 2, further comprising:

forming a tapping connection electrically connected to the second subsection of the contact structure.

6. The method of claim 2, further comprising:

electrically connecting a sense circuit unit to the second subsection of the contact structure, the sense circuit unit being operable to detect an overload condition of the transistor cells based on a signal tapped off and transmitted by the second section of the contact structure.

7. The method of claim 1, further comprising:

forming a further doped region on a second side of the semiconductor substrate opposite the first side,

wherein the doped region and the further doped region have the same conductivity type and a current flow between the doped region and the further doped region is controllable by a potential applied to the gate conductor structures.

8. The method of claim 1, further comprising:

forming plated-through holes outside the cell array which extend through the dielectric layer and electrically connect the gate electrode to one of the gate conductor structures,

wherein the plated-through holes formed outside the cell array and at least one partial layer of the contact structure directly adjoining the dielectric layer are formed from the same material or materials.

9. The method of claim 1, further comprising:

forming the gate conductor structure of each transistor cell in a gate trench which extends, starting from the first surface, into the semiconductor substrate.

10. The method of claim 1, wherein a thickness of the contact structure is at most 300 nanometers and a thickness of the electrode structure is at least one micrometer.

11. The method of claim 1, further comprising:

forming a sense line on the first side of the semiconductor substrate and electrically connected to at least one doped region not connected to the electrode structure; and

forming a sense-source connection electrically connected to the sense line.

12. The method of claim 1, wherein each gate conductor structure extends in the longitudinal direction beyond the gate electrode.

13. The method of claim 1, wherein the first section, the second section and the third section of the contact structure are disposed in the same plane and each separated from the semiconductor substrate by a same thickness of the dielectric layer.

14. The method of claim 1, wherein the interface structure is a contact pad for making external contact with or making a transition to a logic region of the integrated power transistor circuit.