Thin film transistor, method for manufacturing same and semiconductor device comprising said thin film transistor

• US 10,475,934 B2
• Filed: 12/07/2016
• Issued: 11/12/2019
• Est. Priority Date: 12/08/2015
• Status: Active Grant

• Current Assignee: Nara Institute of Science and Technology, National University Corporation, Nissin Electric Company Limited
• Original Assignee: Nara Institute of Science and Technology, National University Corporation
• Inventors: Uraoka, Yukiharu, Yamazaki, Haruka, Fujii, Mami, Takahashi, Eiji
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US16/060,415
• Publication Number:
  US 20190006525A1
• Time in Patent Office: 1,070 Days
• Field of Search: 257 43, 257 40, 257 57, 257 60, 257347, 257E29151, 257E29162, 257E29279, 257E29291, 257E21143, 257E21194, 257E21412, 257E21413, 257E21414, 438104, 438151, 438164, 438303, 438591, 438694, 524516
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor having a high operation speed with a field effect mobility greater than 20 cm²/Vs and a method for manufacturing the same, and a semiconductor device having the same are provided. A thin film transistor in which a gate electrode, a gate insulating film and an oxide semiconductor film are laminated on a substrate, a source region and a drain region are respectively formed in outer portions of the oxide semiconductor film in the width direction, and a channel region is formed in a region between the source region and the drain region; and a source electrode is connected to the source region, while a drain electrode is connected to the drain region. The gate insulating film contains fluorine; and the ratio of the width W of the channel region to the length L thereof, namely W/L is less than 8.

Claims

1. A thin film transistor in which a gate electrode, a gate

insulating film, and an oxide semiconductor film are laminated on a substrate,

a source region and a drain region are formed on both outer sides of the oxide semiconductor film in a width direction,

a channel region is formed in a region between the source region and the drain region,

a source electrode is connected to the source region, and

a drain electrode is connected to the drain region,

wherein fluorine is contained in the gate insulating film, a content of fluorine in the gate insulating film is 1 to 25 at %, a ratio (W/L) of a width W to a length L of the channel region is less than 8, and the thin film transistor has a field effect mobility of greater than 20 cm²/Vs.

2. The thin film transistor according to claim 1,

wherein a ratio (W/L) of a width W to a length L of the channel region is 0.8 or less.

3. The thin film transistor according to claim 1,

wherein the gate insulating film is made of a fluorinated silicon nitride.

4. The thin film transistor according to claim 1,

wherein a hydrogen content of the gate insulating film is 1 at % or less.

5. The thin film transistor according to claim 1,

wherein the oxide semiconductor film is made of any of In—

Ga—

Zn—

O type, In—

Sn—

Zn—

O type, and In—

W—

Zn—

O type amorphous oxides.

6. A semiconductor device including a circuit constituted by the thin film transistor according to claim 1.

7. A method for manufacturing a thin film transistor in which a gate electrode, a gate insulating film, and an oxide semiconductor film are laminated on a substrate,

a source region and a drain region are formed on both outer sides of the oxide semiconductor film in a width direction,

a channel region is formed in a region between the source region and the drain region,

a source electrode is connected to the source region, and

a drain electrode is connected to the drain region, the method comprising:

forming a gate insulating film containing fluorine as the gate insulating film, wherein a content of fluorine in the gate insulating film is 1 to 25 at %; and

forming the source region and the drain region on the oxide semiconductor film so that a ratio (W/L) of a width W to a length L of the channel region is less than 8, wherein the thin film transistor has a field effect mobility of greater than 20 cm²/Vs.

8. The method for manufacturing a thin film transistor according to claim 7,

wherein as the gate insulating film, a gate insulating film made of a fluorinated silicon nitride is formed according to a plasma CVD method using a gas in which silicon tetrafluoride and nitrogen are mixed as a raw material gas.

9. The method for manufacturing a thin film transistor according to claim 8,

wherein an inductively coupled plasma CVD method is used as the plasma CVD method.

10. The method for manufacturing a thin film transistor according to claim 7,

wherein an annealing treatment is performed in an atmosphere containing nitrogen and oxygen after the source region and the drain region are formed on the oxide semiconductor film.

11. The method for manufacturing a thin film transistor according to claim 10,

wherein the annealing treatment is performed at 150 to 450°

C. for 0.5 to 2 hours.