Enhanced channel interleaving for optimized data throughput

• US 10,476,627 B2
• Filed: 05/29/2018
• Issued: 11/12/2019
• Est. Priority Date: 05/22/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Bhushan, Naga, Black, Peter John
• Primary Examiner(s): Nawaz, Asad M
• Assistant Examiner(s): Cairns, Thomas R
• Application Number:
  US15/991,712
• Publication Number:
  US 20180278363A1
• Time in Patent Office: 532 Days
• CPC Class Codes: H04L 1/0002 by adapting the transmission rate
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0007 by modifying the frame length
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0069 Puncturing patterns
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0083 Formatting with frames or packets; Protocol or part of protocol for error control
• CPC Class Codes: H04L 1/18 Automatic repetition systems, e.g. Van Duuren systems
• CPC Class Codes: H04L 5/0048 Allocation of pilot signals, i.e. of signals known to the receiver

Abstract

In a transmission scheme wherein multi-slot packet transmissions to a remote station can be terminated by an acknowledgment signal from the remote station, code symbols can be efficiently packed over the multi-slot packet so that the remote station can easily decode the data payload of the multi-slot packet by decoding only a portion of the multi-slot packet. Hence, the remote station can signal for the early termination of the multi-slot packet transmission, which thereby increases the data throughput of the system.

Claims

1. A method for symbol transmission comprising:

generating a plurality of data symbols and a plurality of parity symbols;

interleaving said plurality of data symbols to form a block of interleaved data symbols;

interleaving said plurality of parity symbols to form a block of interleaved parity symbols separate from the block of interleaved data symbols;

combining the block of interleaved data symbols and the block of interleaved parity symbols to form an output sequence;

transmitting said output sequence over a plurality of slots;

transmitting at least a portion of said plurality of data symbols during a first slot of said plurality of slots; and

terminating said transmitting over said plurality of slots in response to receiving an acknowledgment signal.

2. The method of claim 1, wherein said generating the plurality of data symbols and the plurality of parity symbols comprises turbo encoding said plurality of data symbols.

3. The method of claim 2, wherein said turbo encoding said plurality of data symbols comprises:

generating a first plurality of parity symbols from said plurality of data symbols using a first constituent encoder, wherein the first constituent encoder is a recursive, convolutional encoder;

interleaving said plurality of data symbols using a turbo interleaver;

generating a second plurality of parity symbols from said plurality of interleaved data symbols using a second constituent encoder; and

selectively puncturing and repeating said plurality of data symbols and said plurality of parity symbols.

4. The method of claim 3, wherein said turbo encoding further comprises:

generating a third plurality of parity symbols using said first constituent encoder;

generating a fourth plurality of parity symbols using said second constituent encoder;

interleaving said first and second plurality of parity symbols separately from said third and fourth plurality of parity symbols; and

transmitting each of said first and second plurality of parity symbols before transmitting said third and fourth plurality of parity symbols over said plurality of slots.

5. The method of claim 1, wherein said generating the plurality of data symbols and the plurality of parity symbols comprises convolutional encoding a plurality of data symbols.

6. An apparatus for symbol transmission comprising:

means for generating a plurality of data symbols and a plurality of parity symbols;

means for interleaving said plurality of data symbols to form a block of interleaved data symbols;

means for interleaving said plurality of parity symbols to form a block of interleaved parity symbols separate from the block of interleaved data symbols;

means for combining the block of interleaved data symbols and the block of interleaved parity symbols to form an output sequence;

means for transmitting said output sequence over a plurality of slots;

means for transmitting at least a portion of said plurality of data symbols during a first slot of said plurality of slots; and

means for terminating said transmitting over said plurality of slots in response to receiving an acknowledgment signal.

7. The apparatus of claim 6, wherein said generating the plurality of data symbols and the plurality of parity symbols comprises turbo encoding said plurality of data symbols.

8. The apparatus of claim 7, wherein said means for turbo encoding said plurality of data symbols comprises:

means for generating a first plurality of parity symbols from said plurality of data symbols using a first constituent encoder, wherein the first constituent encoder is a recursive, convolutional encoder;

means for interleaving said plurality of data symbols using a turbo interleaver;

means for generating a second plurality of parity symbols from said plurality of interleaved data symbols using a second constituent encoder; and

selectively puncturing and repeating said plurality of data symbols and said plurality of parity symbols.

9. The apparatus of claim 8, wherein said means for turbo encoding further comprises:

means for generating a third plurality of parity symbols using said first constituent encoder;

means for generating a fourth plurality of parity symbols using said second constituent encoder;

means for interleaving said first and second plurality of parity symbols separately from said third and fourth plurality of parity symbols; and

means for transmitting each of said first and second plurality of parity symbols before transmitting said third and fourth plurality of parity symbols over said plurality of slots.

10. The apparatus of claim 6, wherein said means for generating the plurality of data symbols and the plurality of parity symbols comprises means for convolutional encoding a plurality of data symbols.

11. A computer-readable medium programmed with a set of instructions, which when executed by a processor, cause to perform the steps comprising:

generating a plurality of data symbols and a plurality of parity symbols;

interleaving said plurality of data symbols to form a block of interleaved data symbols;

interleaving said plurality of parity symbols to form a block of interleaved parity symbols separate from the block of interleaved data symbols;

combining the block of interleaved data symbols and the block of interleaved parity symbols to form an output sequence;

transmitting said output sequence over a plurality of slots;

transmitting at least a portion of said plurality of data symbols during a first slot of said plurality of slots; and

terminating said transmitting over said plurality of slots in response to receiving an acknowledgment signal.

12. The computer-readable medium of claim 11, wherein said generating the plurality of data symbols and the plurality of parity symbols comprises turbo encoding said plurality of data symbols.

13. The computer-readable medium of claim 12, wherein said turbo encoding said plurality of data symbols comprises:

generating a first plurality of parity symbols from said plurality of data symbols using a first constituent encoder, wherein the first constituent encoder is a recursive, convolutional encoder;

interleaving said plurality of data symbols using a turbo interleaver;

generating a second plurality of parity symbols from said plurality of interleaved data symbols using a second constituent encoder; and

selectively puncturing and repeating said plurality of data symbols and said plurality of parity symbols.

14. The computer-readable medium of claim 13, wherein said turbo encoding further comprises:

generating a third plurality of parity symbols using said first constituent encoder;

generating a fourth plurality of parity symbols using said second constituent encoder;

interleaving said first and second plurality of parity symbols separately from said third and fourth plurality of parity symbols; and

transmitting each of said first and second plurality of parity symbols before transmitting said third and fourth plurality of parity symbols over said plurality of slots.

15. The computer-readable medium of claim 11, wherein said generating the plurality of data symbols and the plurality of parity symbols comprises convolutional encoding a plurality of data symbols.

16. An apparatus for symbol transmission comprising:

a memory; and

a processor operably connected to the memory, wherein the processor is configured to;

generate a plurality of data symbols and a plurality of parity symbols;

interleave said plurality of data symbols to form a block of interleaved data symbols;

interleave said plurality of parity symbols to form a block of interleaved parity symbols separate from the block of interleaved data symbols;

combine the block of interleaved data symbols and the block of interleaved parity symbols to form an output sequence;

transmit said output sequence over a plurality of slots;

transmit at least a portion of said plurality of data symbols during a first slot of said plurality of slots; and

terminate said transmitting over said plurality of slots in response to receiving an acknowledgment signal.

17. The apparatus of claim 16, wherein the processor is further configured to generate the plurality of data symbols and the plurality of parity symbols by turbo encoding said plurality of data symbols.

18. The apparatus of claim 17, wherein said turbo encoding said plurality of data symbols comprises:

generating a first plurality of parity symbols from said plurality of data symbols using a first constituent encoder, wherein the first constituent encoder is a recursive, convolutional encoder;

interleaving said plurality of data symbols using a turbo interleaver;

generating a second plurality of parity symbols from said plurality of interleaved data symbols using a second constituent encoder; and

selectively puncturing and repeating said plurality of data symbols and said plurality of parity symbols.

19. The apparatus of claim 18, wherein said turbo encoding further comprises:

generating a third plurality of parity symbols using said first constituent encoder;

generating a fourth plurality of parity symbols using said second constituent encoder;

interleaving said first and second plurality of parity symbols separately from said third and fourth plurality of parity symbols; and

transmitting each of said first and second plurality of parity symbols before transmitting said third and fourth plurality of parity symbols over said plurality of slots.

20. The apparatus of claim 16, wherein the processor is further configured to generate the plurality of data symbols and the plurality of parity symbols by convolutional encoding a plurality of data symbols.