Granular dynamic test systems and methods
First Claim
1. A system comprising:
- a global clock input for receiving a global clock associated with circuit testing operations;
a plurality of partitions;
a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the plurality of partitions and a balanced local clock within at least one of the plurality of partitions, wherein the skew tolerant interface includes a first de-skew sub system for a circuit test input path of the at least one of the plurality of partitions and a second de-skew sub-system for a circuit test output path of the at least one of the plurality of partitions.
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Abstract
In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.
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Citations
20 Claims
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1. A system comprising:
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a global clock input for receiving a global clock associated with circuit testing operations; a plurality of partitions; a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the plurality of partitions and a balanced local clock within at least one of the plurality of partitions, wherein the skew tolerant interface includes a first de-skew sub system for a circuit test input path of the at least one of the plurality of partitions and a second de-skew sub-system for a circuit test output path of the at least one of the plurality of partitions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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distributing a first clock to a plurality of partitions; generating a second clock that is locally balanced with at least one of the plurality of partitions; and performing mesochronous synchronization to independently mitigate clock skew constraint between the first clock and the second clock when performing test input and test output operations to and from the at least one of the plurality of partitions. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A system comprising:
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a global clock input for receiving a global clock associated with circuit testing operations; a plurality of partitions; a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the plurality of partitions and a balanced local clock within at least one of the plurality of partitions, wherein the skew tolerant interface includes a first de-skew sub system for a scan test input path of the at least one of the plurality of partitions and a second de-skew sub-system for a scan test output path of the at least one of the plurality of partitions.
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Specification