Granular dynamic test systems and methods

• US 10,481,203 B2
• Filed: 04/03/2017
• Issued: 11/19/2019
• Est. Priority Date: 04/04/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Sarangi, Shantanu, Sonawane, Milind, Balagopala, Adarsh Kalliat, Sanghani, Amit
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/478,176
• Publication Number:
  US 20170205465A1
• Time in Patent Office: 960 Days
• Field of Search: 714700, 714726, 714727, 713503, 713400, 713401, 327293, 327295, 327296, 375354, 375357, 375362
• CPC Class Codes: G01R 31/31726 Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00

Abstract

In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.

Claims

1. A system comprising:

a global clock input for receiving a global clock associated with circuit testing operations;

a plurality of partitions;

a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the plurality of partitions and a balanced local clock within at least one of the plurality of partitions, wherein the skew tolerant interface includes a first de-skew sub system for a circuit test input path of the at least one of the plurality of partitions and a second de-skew sub-system for a circuit test output path of the at least one of the plurality of partitions.

2. The system of claim 1 wherein the plurality of partitions are test partitions.

3. The system of claim 1 wherein the skew tolerant interface crosses a mesochronous boundary and the first de-skew sub system and the second sub system are independent of the at least one of the plurality of partitions and also are independent of skew tolerant interfaces of others of the plurality of partitions.

4. The system of claim 1 wherein the skew tolerant interface includes a first deskew ring buffer in the first de-skew sub system and a second deskew ring buffer in the second de-skew sub system.

5. The system of claim 4 wherein pointers associated with the first deskew ring buffer and the second deskew ring buffer are free-running and depend only on the global clock from outside and the balanced local clock within at least one of the plurality of partitions being pulsed when out of reset.

6. The system of claim 1 wherein a compensation scheme of the skew tolerant interface is fully synchronous and deterministic.

7. The system of claim 1 wherein a compensation scheme of the skew tolerant interface is modeled for Automatic Test Pattern Generation (ATPG) tools using simple pipeline flops.

8. The system of claim 1 wherein the first de-skew sub system and the second de-skew sub system include respective pipelines, a depth of the respective pipelines is dependent on a respective pointer difference for respective read/write portions of the first de-skew sub system and the second de-skew sub system.

9. The system of claim 1 wherein input from the global clock is part of a scan link.

10. A method comprising:

distributing a first clock to a plurality of partitions;

generating a second clock that is locally balanced with at least one of the plurality of partitions; and

performing mesochronous synchronization to independently mitigate clock skew constraint between the first clock and the second clock when performing test input and test output operations to and from the at least one of the plurality of partitions.

11. The method of claim 10 wherein the first clock is an incoming distributed clock and the second clock is a balanced local clock.

12. The method of claim 10 wherein a ring buffer is utilized in the performance of the mesochronous synchronization.

13. The method of claim 12 wherein respective input and output pointers associated with the ring buffers are asynchronously reset.

14. The method of claim 13 wherein the respective input and output pointers associated with the ring buffer are asynchronously de-asserted with the first clock and the second clock off.

15. The method of claim 10 wherein a reset as well as a rest default values are programmable via a test access port.

16. The method of claim 10 wherein after a reset there is a fixed difference in a spread between a write and a read pointer associated with the ring buffer.

17. The method of claim 16 wherein a difference is based on a skew of the first clock and the second clock.

18. The method of claim 17 wherein the difference is used for timing a data path crossings using a multi cycle scheme.

19. The system of claim 10 wherein the plurality of partitions are test partitions.

20. A system comprising:

a global clock input for receiving a global clock associated with circuit testing operations;

a plurality of partitions;

a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the plurality of partitions and a balanced local clock within at least one of the plurality of partitions, wherein the skew tolerant interface includes a first de-skew sub system for a scan test input path of the at least one of the plurality of partitions and a second de-skew sub-system for a scan test output path of the at least one of the plurality of partitions.