Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers

• US 10,481,976 B2
• Filed: 12/27/2017
• Issued: 11/19/2019
• Est. Priority Date: 10/24/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, Louie, Benjamin, El-Baraji, Mourad, Crudele, Lester
• Primary Examiner(s): Butler, Sarai E
• Application Number:
  US15/855,866
• Publication Number:
  US 20190121692A1
• Time in Patent Office: 692 Days
• Field of Search: 714 3
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.

Claims

1. A method for correcting bit defects in a memory array, the method comprising:

determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the distribution of bit-cell resistances comprises a distribution of acceptable high resistance bits and a distribution of acceptable low resistance bits, wherein the margin area is between the distribution of acceptable high resistance bits and acceptable low resistance bits, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous; and

forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits in order to widen a window between the distribution of acceptable high resistance bits and acceptable low resistance bits.

2. The method of claim 1, further comprising:

replacing each short-circuited memory bit-cell with a corresponding redundant bit in a codeword associated with the short-circuited memory bit-cell.

3. The method of claim 1, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are not distinguished by the sense amplifier as either high or low.

4. The method of claim 1, wherein the memory array is a STT-MRAM memory array.

5. The method of claim 3, wherein the determining the margin area comprises:

sliding the reference point in a left direction to establish a margin high reference point and determining bit-cell resistances in the memory array higher than the margin high reference point;

sliding the reference point in a right direction to establish a margin low reference point and determining bit-cell resistances in the memory array lower than the margin low reference point; and

determining bit-cell resistances between the margin high reference point and the margin low reference point to establish the margin area.

6. The method of claim 5, wherein the determining bit-cell resistances between the margin high reference point and the margin low reference point comprises performing an XOR operation.

7. The method of claim 5, wherein a width of the margin area is based on a speed of the sense amplifier.

8. The method of claim 1, wherein the replacing comprises:

determining a position of a short-circuited memory bit-cell in an associated codeword, wherein each codeword comprises a plurality of redundant bits;

mapping a redundant bit of an associated plurality of redundant bits in the associated codeword to the short-circuited memory bit-cell in accordance with the position of the short-circuited memory bit-cell; and

during memory operation, storing a word into the associated codeword wherein a bit is stored in the redundant bit in lieu of the short-circuited bit in accordance with the mapping.

9. The method of claim 8, wherein the mapping is performed in accordance with a mapping scheme.

10. The method of claim 9, wherein in accordance with the mapping scheme, a short-circuited memory bit-cell is replaced with a corresponding redundant bit based on a relative position of the short-circuited memory bit-cell.

11. The method of claim 1, wherein to replace each short-circuited memory bit-cell with a corresponding redundant bit in a codeword, the processor is configured to:

determine a position of a short-circuited memory bit-cell in an associated codeword, wherein each codeword comprises a plurality of redundant bits;

map a redundant bit of an associated plurality of redundant bits in the associated codeword to the short-circuited memory bit-cell in accordance with the position of the short-circuited memory bit-cell; and

during memory operation, store a word into the associated codeword wherein a bit is stored in the redundant bit in lieu of the short-circuited bit in accordance with the mapping.

12. An apparatus for correcting bit defects, the apparatus comprising:

a processor;

a memory array comprising a plurality of codewords, wherein each codeword comprises a respective plurality of redundant bits, and wherein the processor is configured to;

determine a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the distribution of bit-cell resistances comprises a distribution of acceptable high resistance bits and a distribution of acceptable low resistance bits, wherein the margin area is between the distribution of acceptable high resistance bits and acceptable low resistance bits, wherein the bit-cell resistances of memory bit-cells associated with the margin area are not distinguished by a sense amplifier as either high or low; and

force the bit-cell resistances of memory bit-cells associated with the margin area to short circuits in order to widen a window between the distribution of acceptable high resistance bits and acceptable low resistance bits.

13. The apparatus of claim 12, wherein the processor is further configured to:

replace each short-circuited memory bit-cell with a corresponding redundant bit in a codeword associated with the short-circuited memory bit-cell.

14. The apparatus of claim 13, wherein the memory array is a STT-MRAM memory array.

15. The apparatus of claim 12, wherein to determine the margin area, the processor is configured to:

slide a reference point in a left direction to establish a margin high reference point and determining bit-cell resistances in the memory array higher than the margin high reference point;

slide the reference point in a right direction to establish a margin low reference point and determining bit-cell resistances in the memory array lower than the margin low reference point; and

determine bit-cell resistances between the margin high reference point and the margin low reference point to establish the margin area.

16. The apparatus of claim 15, wherein to determine bit-cell resistances between the margin high reference point and the margin low reference point the processor is configured to perform an XOR operation.

17. The apparatus of claim 15, wherein a width of the margin area is based on a speed of the sense amplifier.

18. A method for correcting bit defects in a memory array, the method comprising:

determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous, wherein ambiguous bit-cells are not distinguished as high or low bits;

forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits.

19. The method of claim 18, further comprising:

replacing each short-circuited memory bit-cell with a corresponding redundant bit in a codeword associated with the short-circuited memory bit-cell.

20. The method of claim 18, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier.

21. The method of claim 18, wherein the memory array is a STT-MRAM memory array.

22. The method of claim 18, wherein the determining the margin area comprises:

sliding a reference point in a left direction to establish a margin high reference point and determining bit-cell resistances in the memory array higher than the margin high reference point;

sliding the reference point in a right direction to establish a margin low reference point and determining bit-cell resistances in the memory array lower than the margin low reference point; and

determining bit-cell resistances between the margin high reference point and the margin low reference point to establish the margin area.

23. The method of claim 22, wherein the determining bit-cell resistances between the margin high reference point and the margin low reference point comprises performing an XOR operation.

24. The method of claim 22, wherein a width of the margin area is based on a speed of the sense amplifier.