Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers
First Claim
1. A method for correcting bit defects in a memory array, the method comprising:
- determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the distribution of bit-cell resistances comprises a distribution of acceptable high resistance bits and a distribution of acceptable low resistance bits, wherein the margin area is between the distribution of acceptable high resistance bits and acceptable low resistance bits, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous; and
forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits in order to widen a window between the distribution of acceptable high resistance bits and acceptable low resistance bits.
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Abstract
A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.
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Citations
24 Claims
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1. A method for correcting bit defects in a memory array, the method comprising:
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determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the distribution of bit-cell resistances comprises a distribution of acceptable high resistance bits and a distribution of acceptable low resistance bits, wherein the margin area is between the distribution of acceptable high resistance bits and acceptable low resistance bits, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous; and forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits in order to widen a window between the distribution of acceptable high resistance bits and acceptable low resistance bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus for correcting bit defects, the apparatus comprising:
- a processor;
a memory array comprising a plurality of codewords, wherein each codeword comprises a respective plurality of redundant bits, and wherein the processor is configured to;
determine a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the distribution of bit-cell resistances comprises a distribution of acceptable high resistance bits and a distribution of acceptable low resistance bits, wherein the margin area is between the distribution of acceptable high resistance bits and acceptable low resistance bits, wherein the bit-cell resistances of memory bit-cells associated with the margin area are not distinguished by a sense amplifier as either high or low; and
force the bit-cell resistances of memory bit-cells associated with the margin area to short circuits in order to widen a window between the distribution of acceptable high resistance bits and acceptable low resistance bits. - View Dependent Claims (13, 14, 15, 16, 17)
- a processor;
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18. A method for correcting bit defects in a memory array, the method comprising:
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determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous, wherein ambiguous bit-cells are not distinguished as high or low bits; forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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Specification