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Phase change memory device

  • US 10,482,954 B2
  • Filed: 08/25/2017
  • Issued: 11/19/2019
  • Est. Priority Date: 07/27/2006
  • Status: Active Grant
First Claim
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1. A memory system, comprising:

  • a memory array comprising multiple memory cells, each coupled to a data bitline, the memory cells arranged in groups with the memory cells of each group coupled to a single wordline;

    multiple reference cells, each reference cell connected to a reference bitline, with at least two reference cells associated with each group of memory cells; and

    a current/voltage converter connected to the data bitlines and reference bitlines through data bitline switches and reference bitline switches, each of the reference bitline switches being sequentially and alternately operated, during a read operation in a respective group, to sequentially and alternately direct a reference current from the respective reference cell to the current/voltage converter.

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