Semiconductor device having a large area interconnect or pad

• US 10,483,223 B2
• Filed: 08/09/2017
• Issued: 11/19/2019
• Est. Priority Date: 08/10/2016
• Status: Expired due to Fees

• Current Assignee: Ablic Inc. (Minebea Mitsumi, Inc.)
• Original Assignee: Ablic Inc. (Minebea Mitsumi, Inc.)
• Inventors: Utsunomiya, Hiroyuki
• Primary Examiner(s): Gondarenko, Natalia A
• Application Number:
  US15/672,578
• Publication Number:
  US 20180047684A1
• Time in Patent Office: 832 Days
• Field of Search: 257774, 257775, 257776, 257758, 257773, 257734, 257377, 257508, 257750, 257762, 257178, 438638, 438619, 438637, 438667, 438672, 438687, 438926, 438622
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/03622 using masks
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/351 Thermal stress

Abstract

A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

an insulating film on a surface of the semiconductor substrate;

a first interconnect on the insulating film and having a first width in a first direction and a second width in a second direction, the second direction orthogonal to the first direction;

a second interconnect having a length in the second direction of equal to or less than 20 microns and having a third width in the first direction, wherein the third width is smaller than the first width and the second width, and the second interconnect is coupled to the first interconnect at a first coupling portion between the first interconnect and one end of the second interconnect, the first coupling portion extending in the first direction;

a slit in the first interconnect spaced away from the first coupling portion by a length of equal to or less than 20 microns, and having a fourth width that is half or more of the third width; and

a third interconnect coupled to a terminal end of the second interconnect on an opposite side to the first coupling portion, wherein the third interconnect comprises a same layer as the first interconnect and the second interconnect and extends along the first direction.

2. The semiconductor device according to claim 1, further comprising a plurality of slits extending in the first direction, at least two of which extend along a common center line in the first direction.

3. The semiconductor device according to claim 1;

wherein the second interconnect comprises a plurality of second interconnects on one side of the first interconnect, and

wherein the slit comprises a plurality of slits each along the first coupling portion between the first interconnect and the one end of each of the plurality of second interconnects.

7. The semiconductor device according to claim 1, wherein the slit is along a line extending from the second interconnect in the second direction.

8. The semiconductor device according to claim 2, wherein the slit is along a line extending from the second interconnect in the second direction.

4. A semiconductor device, comprising:

a semiconductor substrate;

an insulating film on a surface of the semiconductor substrate;

a pad on the insulating film and having a first width in a first direction and a second width in a second direction, the second direction orthogonal to the first direction;

a second interconnect having a length in the second direction of equal to or less than 20 microns and having a third width in the first direction, wherein the third width is smaller than the first width and the second width, and the second interconnect is coupled to the pad at a first coupling portion between the pad and one end of the second interconnect, the first coupling portion extending in the first direction;

a slit in the pad at a location away from the first coupling portion by a length of equal to or less than 20 microns, and having a fourth width which is half or more of the third width; and

a third interconnect coupled to a terminal end of the second interconnect on an opposite side to the one end and extending along the first direction,

wherein the third interconnect comprises a same layer as the pad and the second interconnect.

5. The semiconductor device according to claim 4, further comprising a plurality of slits in the first direction, at least two of which extend along a common center line in the first direction.

6. The semiconductor device according to claim 4;

wherein the second interconnect comprises a plurality of second interconnects on one side of the pad, and

wherein the slit comprises a plurality of slits each along the first coupling portion between the pad and the one end of each of the plurality of second interconnects.