Semiconductor carrier with vertical power FET module

• US 10,483,260 B2
• Filed: 08/14/2017
• Issued: 11/19/2019
• Est. Priority Date: 06/24/2010
• Status: Active Grant

• Current Assignee: L. Pierre De Rochemont
• Original Assignee: L. Pierre De Rochemont
• Inventors: de Rochemont, L. Pierre
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US15/675,939
• Publication Number:
  US 20180190647A1
• Time in Patent Office: 827 Days
• CPC Class Codes: H01F 17/06 with core substantially closed in itself, e.g. toroid
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 30/16 Toroidal transformers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 3/28 using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
• CPC Class Codes: Y10T 428/12493 Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]

Abstract

A monolithic power management module provides a chip carrier with surfaces, ground traces, signal and power interconnects; a three dimensional FET formed on the chip carrier to modulate currents through the carrier or on the carrier surface; a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the FET and having a first winding connected to the FET, and a plurality of passive ceramic components formed on the chip carrier surface.

Claims

1. A monolithic power management module, comprising:

a chip carrier further comprising surfaces, ground traces, signal and power interconnects;

a three dimensional FET formed on the chip carrier to modulate currents through the chip carrier or on the surfaces;

a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the three dimensional FET and having a first winding connected to the three dimensional FET, and

a plurality of passive ceramic components formed on the chip carrier surfaces including clock circuitry in a form of an LCR resonator further comprising an inductor coil, a capacitive element and a resistive element; and

wherein the three dimensional FET includes an elongated gate electrode comprising a conductor that forms a resonant transmission line by configuring the conductor to form a serpentine electrode that contains a capacitive element determined by charge-collected beneath the gate, a resistive dement determined by the conductor, length and cross-sectional area, of the conductor used to form the serpentine electrode, and an Inductive element formed by half-turns that loop the serpentine electrode winding back upon itself.

2. The module of claim 1, wherein the chip carrier is a semiconducting substrate comprising a plurality of active components formed on or in the carrier.

3. The module of claim 1, further comprising one or more semiconductor die mounted on the carrier that are electrically connected with the power management module.

4. The module of claim 2, further comprising a semiconducting substrate that contains a variety of low-level sensing, latching and bus circuitry integrated on or into its surface.

5. The module of claim 1, wherein the clock circuitry comprises a high-Q LCR resonator encapsulated within amorphous silica.

6. The module of claim 1, wherein the clock circuitry comprises a high-Q LCR resonator formed on an amorphous silica block.

7. The module of claim 6, wherein the chip carrier is a semiconducting substrate that further comprises a phase-locked loop array mounted on or embedded within the chip carrier.

8. The module of claim 7, wherein the self-resonance frequency of the high-Q LCR resonator is altered by a switching element integrated into the chip carrier semiconductor substrate that routes the timing signal through different turns of the inductor coil.

9. The module of claim 3, wherein the passive ceramic components maintain a tolerance that varies ±

1% from their specified performance value over standard operating temperatures.

10. The module of claim 9, wherein the semiconductor die mounted on the carrier comprise fewer redundant transistor assemblies in the semiconductor die than needed when the semiconductor die are electrically connected to interconnect circuitry generating signals tuned by loose tolerance components.

11. The module of claim 10, wherein the chip carrier is a semiconducting chip carrier comprising active circuitry embedded within the carrier substrate.