Semiconductor device and manufacturing method therefor

• US 10,483,263 B2
• Filed: 05/24/2017
• Issued: 11/19/2019
• Est. Priority Date: 06/01/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Zhou, Fei
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Newton, Valerie N
• Application Number:
  US15/603,754
• Publication Number:
  US 20170352663A1
• Time in Patent Office: 909 Days
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first insulator layer; a second insulator layer covering the fin; a plurality of pseudo gate structures on the second insulator layer, where each pseudo gate structure wraps a part of the fin, where each pseudo gate structure includes a pseudo gate located on the second insulator layer, the plurality of pseudo gate structures includes at least a first pseudo gate structure and a second pseudo gate structure that are spaced from each other, the second pseudo gate structure is located at an edge corner of the fin, and a part of the second pseudo gate structure is on the first insulator layer; spacers, on the first insulator layer and the second insulator layer, at two sides of each of the plurality of pseudo gate structures; and a source or a drain located among the plurality of pseudo gate structures. The present invention can improve reliability of the device.

Claims

1. A manufacturing method for a semiconductor device, comprising:

providing a substrate structure, wherein the substrate structure comprises;

a semiconductor substrate;

a single fin protruding from the semiconductor substrate, wherein trenches are formed on sides of the fin;

a pad insulator layer for padding the trenches;

a first insulator layer separately formed from the pad insulator layer and partially filling the trenches, wherein the single fin protrudes from the first insulator layer; and

a second insulator layer covering the single fin;

forming a plurality of pseudo gate structures on the second insulator layer, wherein each pseudo gate structure wraps a part of the single fin, wherein each pseudo gate structure comprises a pseudo gate located on the second insulator layer, wherein the plurality of pseudo gate structures comprises at least a first pseudo gate structure, a second pseudo gate structure, and a third pseudo gate structure that are spaced from each other, and wherein the second pseudo gate structure and the third pseudo gate structure are located at two opposite edge corners of the single fin and the first pseudo gate structure is a only pseudo gate structure disposed between the second pseudo gate structure and the third pseudo gate structure, and a first part of each of the second pseudo gate structure and the third pseudo gate is on and in direct contact with the first insulator layer and a second part of each of the second pseudo gate structure and the third pseudo gate structure is on and in direct contact with the second insulator layer;

forming, above the first insulator layer and the second insulator layer, spacers at two sides of each of the second pseudo gate structure and the third pseudo gate structure, where a bottom face of one of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the first insulator layer whereas a bottom face of another of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the second insulator layer;

etching, after forming the spacers, the second insulator layer and at least a part of the single fin that are not covered by the spacers and the pseudo gates, to form recesses in the single fin; and

forming at least one source or drain in the recesses.

2. The manufacturing method for a semiconductor device according to claim 1, wherein the step of forming recesses comprises:

forming, in the single fin, a first recess located between the first pseudo gate structure and the second pseudo gate structure and forming a second recess located between the first pseudo gate structure and the third pseudo gate structure through etching.

3. The manufacturing method for a semiconductor device according to claim 2, wherein the step of forming at least one source or drain in the recess comprises:

forming a source in the first recess and forming a drain in the second recess.

4. The manufacturing method for a semiconductor device according to claim 1, wherein material of the pseudo gates comprises polysilicon.

5. The manufacturing method for a semiconductor device according to claim 1, further comprising forming a hard mask layer on each of the pseudo gate structures, wherein material of the hard mask layer comprises silicon nitride.

6. The manufacturing method for a semiconductor device according to claim 1, wherein the second pseudo gate structure is spaced from the first pseudo gate structure for a first distance, wherein the first distance ranges from 60 nm to 100 nm.

7. The manufacturing method for a semiconductor device according to claim 1, wherein the third pseudo gate structure is spaced from the first pseudo gate structure for a second distance, wherein the second distance ranges from 60 nm to 100 nm.

8. The manufacturing method for a semiconductor device according to claim 5, further comprising:

forming an interlayer dielectric layer to cover the substrate structure after the source or the drain is formed;

etching back the interlayer dielectric layer, to expose an upper surface of the hard mask layer;

removing the hard mask layer, the pseudo gates, and a part of the second insulator layer, so as to form openings; and

forming gate structures in the opening.

9. The manufacturing method for a semiconductor device according to claim 8, wherein each of the gate structures comprises:

a gate insulator layer that is on the single fin and wraps a part of the single fin, and a gate on the gate insulator layer.

10. The manufacturing method for a semiconductor device according to claim 1, wherein

the single fin is an N-well region, and material of the at least one source or the drain comprises silicon germanium;

or

the single fin is a P-well region, and material of the at least one source or the drain comprises silicon carbide.

11. The manufacturing method for a semiconductor device according to claim 1, wherein the semiconductor substrate comprises two single fins, with a first single fin for forming a PMOS device and a second single fin for forming an NMOS device, and

wherein material of the at least one source or the drain on the first single fin comprises silicon germanium;

and material of the at least one source or the drain on the second single fin comprises silicon carbide.

12. A semiconductor device, comprising:

a semiconductor substrate;

a single fin protruding from the semiconductor substrate, wherein trenches are formed on sides of the single fin;

a pad insulator layer for padding the trenches;

a first insulator layer separately formed from the pad insulator layer and partially filling the trenches, wherein the single fin protrudes from the first insulator layer;

a second insulator layer covering the single fin;

a plurality of pseudo gate structures on the second insulator layer, wherein each pseudo gate structure wraps a part of the single fin, wherein each pseudo gate structure comprises a pseudo gate located on the second insulator layer, wherein the plurality of pseudo gate structures comprises at least a first pseudo gate structure, a second pseudo gate structure, and a third pseudo gate structure that are spaced from each other, and wherein the second pseudo gate structure and the third pseudo gate structure are located at two opposite edge corners of the single fin and the first pseudo gate structure is a only pseudo gate structure disposed between the second pseudo gate structure and the third pseudo gate structure, and a first part of each of the second pseudo gate structure and the third pseudo gate is on and in direct contact with the first insulator layer and a second part of each of the second pseudo gate structure and the third pseudo gate structure is on and in direct contact with the second insulator layer;

spacers at two sides of each of the second pseudo gate structure and the third pseudo gate structure, where a bottom face of one of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the first insulator layer whereas a bottom face of another of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the second insulator layer; and

at least one source or drain on the single fin and located among the plurality of pseudo gate structures.

13. The semiconductor device according to claim 12, wherein material of the pseudo gates comprises polysilicon.

14. The semiconductor device according to claim 12, further comprising a hard mask layer on each of the pseudo gate structures wherein material of the hard mask layer comprises silicon nitride.

15. The semiconductor device according to claim 12, wherein the second pseudo gate structure is spaced from the first pseudo gate structure for a first distance, wherein the first distance ranges from 60 nm to 100 nm.

16. The semiconductor device according to claim 12, wherein the third pseudo gate structure is spaced from the first pseudo gate structure for a second distance, wherein the second distance ranges from 60 nm to 100 nm.

17. The semiconductor device according to claim 12, wherein the at least one source or drain comprises a source located between the first pseudo gate structure and the second pseudo gate structure and

a drain located between the first pseudo gate structure and the third pseudo gate structure.

18. The semiconductor device according to claim 12, wherein

the single fin is an N-well region, and material of the at least one source or the drain comprises silicon germanium;

or

the single fin is a P-well region, and material of the at least one source or the drain comprises silicon carbide.

19. The semiconductor device according to claim 12, wherein the semiconductor device comprises two single fins, with a first single fin for forming a PMOS device and a second single fin for forming an NMOS device,

wherein material of the at least one source or the drain on the first single fin comprises silicon germanium;

and

wherein material of the at least one source or the drain on the second single fin comprises silicon carbide.