Semiconductor device and manufacturing method thereof

• US 10,483,290 B2
• Filed: 01/28/2019
• Issued: 11/19/2019
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Au, Bac H
• Application Number:
  US16/259,121
• Publication Number:
  US 20190157307A1
• Time in Patent Office: 295 Days
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.

Claims

1. A semiconductor device comprising a pixel portion, the pixel portion comprising:

a transistor comprising;

a first conductive layer;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer comprising In, Ga, and Zn over the first insulating layer; and

a second conductive layer and a third conductive layer each electrically connected to the oxide semiconductor layer; and

a pixel electrode electrically connected to the transistor,

wherein the first conductive layer serves as a gate electrode of the transistor and a gate wiring,

wherein the second conductive layer serves as one of a source electrode and a drain electrode of the transistor and a source wiring,

wherein the third conductive layer serves as the other of the source electrode and the drain electrode of the transistor,

wherein the first conductive layer and the second conductive layer intersect with each other in a cross shape and overlap each other in a first region,

wherein a first transparent conductive layer comprising In, Zn, and oxygen overlaps the first region, and

wherein a width of a region of the first conductive layer not overlapping with the first region and not overlapping with the oxide semiconductor layer is different from a width of the first conductive layer in the first region.

2. A semiconductor device comprising a pixel portion, the pixel portion comprising:

a transistor comprising;

a first conductive layer;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer comprising In, Ga, and Zn over the first insulating layer; and

a second conductive layer and a third conductive layer each electrically connected to the oxide semiconductor layer;

a pixel electrode electrically connected to the transistor; and

a liquid crystal layer over the pixel electrode,

wherein the first conductive layer serves as a gate electrode of the transistor and a gate wiring,

wherein the second conductive layer serves as one of a source electrode and a drain electrode of the transistor and a source wiring,

wherein the third conductive layer serves as the other of the source electrode and the drain electrode of the transistor,

wherein the first conductive layer and the second conductive layer intersect with each other in a cross shape and overlap each other in a first region,

wherein a first transparent conductive layer comprising In, Zn, and oxygen overlaps the first region, and

wherein a width of a region of the first conductive layer not overlapping with the first region and not overlapping with the oxide semiconductor layer is different from a width of the first conductive layer in the first region.