Transistor array panel, including a source connecting member and a drain connecting member manufacturing method thereof, and display device including the same

• US 10,483,340 B2
• Filed: 04/06/2017
• Issued: 11/19/2019
• Est. Priority Date: 04/07/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kwon, Hyuk Soon
• Primary Examiner(s): Henry, Caleb E
• Application Number:
  US15/481,273
• Publication Number:
  US 20170294498A1
• Time in Patent Office: 957 Days
• Field of Search: 257 40
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/166 using selective deposition, e.g. using a mask
• CPC Class Codes: H10K 71/231 by etching of existing layers

Abstract

A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.

Claims

1. A transistor display panel comprising:

a substrate;

a first transistor disposed on the substrate; and

a pixel electrode connected to the first transistor,

wherein the first transistor includes;

a first semiconductor on the substrate,

a first insulating layer covering the first semiconductor,

a first gate electrode on the first insulating layer overlapping the first semiconductor,

a first connecting member disposed on the first insulating layer and connected to the first semiconductor, the first connecting member including a first source connecting member and a first drain connecting member,

a second insulating layer covering the first gate electrode, the first source connecting member and the first drain connecting member, and

a first source electrode and a first drain electrode disposed on the second insulating layer,

wherein the first gate electrode includes at least three layers and the first connecting member includes at least two layers,

wherein the first source electrode is connected to the first source connecting member,

wherein the first semiconductor includes a first channel, and a first source region and a first drain region disposed at respective sides of the first channel, and

wherein the first source region and the first drain region are respectively connected to the first source connecting member and the first drain connecting member.

2. The transistor display panel of claim 1, wherein

the first gate electrode includes a first main gate layer, and a first upper gate layer and a first lower gate layer respectively disposed on and under the first main gate layer.

3. The transistor display panel of claim 2, wherein

the first source connecting member includes a first main source connecting layer and a first lower source connecting layer disposed thereunder, and

the first drain connecting member includes a first main drain connecting layer and a first lower drain connecting layer disposed thereunder.

4. The transistor display panel of claim 3, wherein

the first main source connecting layer and the first main drain connecting layer are disposed on the same layer as the first main gate layer.

5. The transistor display panel of claim 1, further comprising

a lower electrode under the first semiconductor and connected to the first source connecting member,

a buffer layer covering the lower electrode,

wherein the first source connecting member is connected to the lower electrode through an opening of the buffer layer and the first insulating layer.

6. The transistor display panel of claim 1, further comprising:

a scan line disposed on the substrate;

a data line crossing the scan line; and

a second transistor connected to the scan line and the data line,

wherein the second transistor includes

a second semiconductor disposed on the same layer as the first semiconductor,

a second gate electrode overlapping the second semiconductor, and

a second source connecting member and a second drain connecting member disposed on the same layer as the second gate electrode and connected to the second semiconductor,

wherein the second gate electrode includes at least three layers, and the first source connecting member and the first drain connecting member include at least two layers.

7. The transistor display panel of claim 6, wherein

the first semiconductor and the second semiconductor include an oxide semiconductor material.

8. A display device comprising:

a substrate;

a first transistor disposed on the substrate; and

a light-emitting diode element connected to the first transistor,

wherein the first transistor includes

a lower electrode disposed on the substrate,

a first semiconductor overlapping the lower electrode,

a first insulating layer covering the first semiconductor,

a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor,

a first connecting member disposed on the first insulating layer and connected to the first semiconductor, the first connecting member including a first source connecting member and a first drain connecting member,

a second insulating layer covering the first gate electrode, the first source connecting member and the first drain connecting member, and

a first source electrode and a first drain electrode disposed on the second insulating layer,

wherein the first gate electrode includes at least three layers, the first connecting member includes at least two layers, and the first connecting member is connected to the lower electrode,

wherein the first source electrode is connected to the first source connecting member,

wherein the first semiconductor includes a first channel, and a first source region and a first drain region disposed at respective sides of the first channel, and

wherein the first source region and the first drain region are respectively connected to the first source connecting member and the first drain connecting member.

9. The display device of claim 8, wherein:

the first gate electrode includes a first main gate layer, and a first upper gate layer and a first lower gate layer respectively disposed on and under the first main gate layer;

the first source connecting member includes a first main source connecting layer and a first lower source connecting layer disposed thereunder; and

the first drain connecting member includes a first main drain connecting layer and a first lower drain connecting layer disposed thereunder.

10. The display device of claim 9, further comprising:

a scan line disposed on the substrate;

a data line crossing the scan line; and

a second transistor connected to the scan line and the data line,

wherein the second transistor includes;

a second semiconductor disposed on the same layer as the first semiconductor,

a second gate electrode overlapping the second semiconductor, and

a second source connecting member and a second drain connecting member disposed on the same layer as the second gate electrode and connected to the second semiconductor, and

wherein the second gate electrode includes at least three layers, and the first source connecting member and the first drain connecting member include at least two layers.

11. The display device of claim 10, wherein

the first semiconductor and the second semiconductor include an oxide semiconductor material.

12. The display device of claim 8, wherein

the light-emitting diode element includes an organic light emitting diode.