Method of fabricating a power semiconductor device

• US 10,483,359 B2
• Filed: 07/28/2017
• Issued: 11/19/2019
• Est. Priority Date: 05/16/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Henson, Timothy D., Kelkar, Kapil, Radic, Ljubo
• Primary Examiner(s): Fan, Michele
• Application Number:
  US15/663,329
• Publication Number:
  US 20170330942A1
• Time in Patent Office: 844 Days
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.

Claims

1. A method of fabricating a power semiconductor device, said method comprising:

forming a gate trench in a semiconductor substrate, said gate trench including a gate electrode; and

forming a field plate trench structure in said substrate separate from said gate trench, wherein forming said field plate trench structure comprises;

forming an upper trench situated over a lower trench in said substrate, said upper trench being wider than said lower trench and extending deeper into said substrate than said gate trench, a width of said lower trench being greater than one half a width of said upper trench;

forming a trench dielectric in said lower trench and on sidewalls of said upper trench, said trench dielectric filling completely said lower trench; and

forming a field plate electrode within said trench dielectric;

wherein said trench dielectric is formed such that a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said upper trench.

2. The method of claim 1, further comprising:

forming a sacrificial layer in said upper trench prior to said forming said lower trench;

etching said sacrificial layer to form spacers on said sidewalls of said upper trench.

3. The method of claim 2, further comprising removing said spacers after said forming said lower trench.

4. The method of claim 2, wherein forming said sacrificial layer in said upper trench prior to said forming said lower trench comprises:

isotropically depositing said sacrificial layer over a hard mask dielectric on said substrate and into said upper trench, without filling said upper trench.

5. The method of claim 2, wherein forming said lower trench in said substrate comprises:

etching into said substrate in a region below said upper trench and unprotected by said spacers, so that a width of said spacers determines a width of said lower trench.

6. The method of claim 1, wherein said bottom thickness is at least 120% greater than said sidewall thickness.

7. The method of claim 1, wherein said sidewall thickness tapers from a top to a bottom of said sidewalls.

8. The method of claim 1, wherein said trench dielectric comprises TEOS.