Method to induce strain in 3-D microfabricated structures

• US 10,483,393 B2
• Filed: 10/31/2017
• Issued: 11/19/2019
• Est. Priority Date: 07/29/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Loubet, Nicolas, Morin, Pierre
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US15/798,976
• Publication Number:
  US 20180069121A1
• Time in Patent Office: 749 Days
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Claims

1. A device, comprising:

a substrate having a first portion and a second portion extending away from the first portion, the second portion having a first length in a first direction and a first width in a second direction orthogonal to the first direction;

a microfabricated structure on the substrate, the microfabricated structure having a fin including;

the second portion of the substrate;

a strain-inducing layer on the second portion of the substrate, the strain-inducing layer having a second length in the first direction and a second width in the second direction, the first length approximately equal to the second length and the first width approximately equal to the second width; and

a semiconductor layer on the strain-inducing layer.

2. The device of claim 1 wherein the semiconductor layer includes a strained channel.

3. The device of claim 1 wherein the strain-inducing layer includes at least one of silicon germanium and silicon carbide.

4. The device of claim 1 wherein the microfabricated structure includes an insulating layer on a portion of the semiconductor layer.

5. The device of claim 4 wherein the microfabricated structure includes a gate electrode on the insulating layer.

6. The device of claim 5 wherein the gate electrode includes a first portion and a second portion, the first portion of the gate electrode on a first side of the second portion of the substrate and a second portion of the gate electrode on a second side of the second portion of the substrate, the first side opposite the second side.

7. The device of claim 1 wherein the semiconductor layer has a third length in the first direction and a third width in the second direction, the first length approximately equal to the third length and the first width approximately equal to the third width.

8. A device, comprising:

a substrate having a first portion with a first surface and a second portion with a second surface spaced apart from the first surface; and

a semiconductor structure extending away from the second surface of the substrate, the semiconductor structure including;

a strain-inducing layer having a first surface on the second surface of the substrate and a second surface; and

a semiconductor layer having a first surface on the second surface of the strain-inducing layer and a second surface,

wherein the second portion of the substrate has the same length and width as the strain-inducing layer and the semiconductor layer.

9. The device of claim 8 wherein a distance between the first surface of the semiconductor layer and the second surface of the semiconductor layer is less than a distance between the first surface of the strain-inducing layer and the second surface of the strain-inducing layer.

10. The device of claim 8 wherein the strain-inducing layer includes silicon germanium or silicon carbide.

11. The device of claim 8 further including an insulating layer on a portion of the semiconductor layer.

12. The device of claim 11 further including a gate electrode on the insulating layer.

13. The device of claim 12 wherein a portion of the gate electrode is on the first surface of the substrate.

14. A device, comprising:

a substrate having a raised portion;

a fin on the raised portion of the substrate, the fin including;

a first semiconductor layer on the raised portion of the substrate; and

a second semiconductor layer that is strained on the first semiconductor layer; and

a gate insulator contacting sidewalls of the first semiconductor layer and the second semiconductor layer.

15. The device of claim 14 wherein the first semiconductor layer is relaxed.

16. The device of claim 14 further including a dielectric layer adjacent to at least a portion of the fin and the raised portion of the substrate.

17. The device of claim 16 further including a gate electrode adjacent to the dielectric layer.

18. The device of claim 14 wherein the second semiconductor layer includes a strained channel.

19. The device of claim 14 wherein the first semiconductor layer includes silicon germanium or silicon carbide.

20. A device, comprising:

a substrate having a raised portion;

a dielectric layer over the substrate and surrounding the raised portion;

a fin on the raised portion of the substrate, the fin including;

a first semiconductor layer on the raised portion of the substrate, wherein the first semiconductor layer is protruded above the dielectric layer; and

a second semiconductor layer that is strained on the first semiconductor layer; and

a gate structure adjacent to sidewalls of the first semiconductor layer and the second semiconductor layer.

21. The device of claim 20, wherein the raised portion of the substrate has a width the same as a width of the first semiconductor layer.