Semiconductor devices with depleted heterojunction current blocking regions

• US 10,483,719 B2
• Filed: 07/12/2017
• Issued: 11/19/2019
• Est. Priority Date: 07/13/2016
• Status: Active Grant

• Current Assignee: Sdphotonics, LLC, University of Central Florida Research Foundation Inc. (State University System of Florida)
• Original Assignee: University of Central Florida Research Foundation Inc. (State University System of Florida)
• Inventors: Deppe, Dennis G.
• Primary Examiner(s): Ho, Anthony
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US15/648,235
• Publication Number:
  US 20180019302A1
• Time in Patent Office: 860 Days
• Field of Search: None
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01S 5/18308 having a special structure for lateral current or light confinement
• CPC Class Codes: H01S 5/18358 containing spacer layers to adjust the phase of the light wave in the cavity
• CPC Class Codes: H01S 5/2063 obtained by particle bombardment

Abstract

A semiconductor device includes an upper and lower mirror. At least one active region for light generation is between the upper and lower mirror. At least one cavity spacer layer is between at least one of the upper and lower mirror and the active region. The device includes an inner mode confinement region and an outer current blocking region. A depleted heterojunction current blocking region (DHCBR) including a depleting impurity is within the outer current blocking region of ≥1 of the upper mirror, lower mirror, and the first active region. A middle layer including a conducting channel is within the inner mode confinement region that is framed by the DHCBR. The DHCBR forces current flow into the conducting channel during normal operation of the light source.

Claims

1. A semiconductor heterostructure device, comprising:

a middle layer including an inner conducting channel and an outer current blocking region, wherein said middle layer comprises an epitaxially regrown interface;

a depleted heterojunction current blocking region (DHCBR) within said outer current blocking region,

wherein said DHCBR includes a depleting impurity region comprising at least one depleting impurity which increases a depletion of said DHCBR so that said DHCBR forces current to flow into said conducting channel during electrical biasing under normal operation of said semiconductor heterostructure device, and

wherein said depleting impurity has a maximum concentration that is within 700 Å

of said epitaxially regrown interface.

2. The semiconductor heterostructure device of claim 1, wherein said depleting impurity region comprises silicon or oxygen.

3. The semiconductor heterostructure device of claim 1, wherein said middle layer comprises AlAs.

4. The semiconductor heterostructure device of claim 1, wherein said middle layer comprises a mesa.

5. The semiconductor heterostructure device of claim 1, wherein said DHCBR includes a first depleting impurity specie and a second depleting impurity specie.

6. The semiconductor heterostructure device of claim 5, wherein said first depleting impurity specie is beryllium and said second depleting impurity specie is oxygen.

7. A semiconductor vertical resonant cavity light source, comprising:

an upper mirror comprising alternating low refractive index mirror layers and high refractive index mirror layers and a lower mirror comprising alternating low refractive index mirror layers and high refractive index mirror layers;

at least one active region for light generation between said upper mirror and said lower mirror;

at least one cavity spacer layer between at least one of said upper mirror and said lower mirror and said active region;

said light source including an inner mode confinement region and an outer current blocking region;

a depleted heterojunction current blocking region (DHCBR) including a depleting impurity region comprising at least one depleting impurity region within said outer current blocking region of at least one of said upper mirror, said lower mirror, and said active region, and

a middle layer including a conducting channel within said inner mode confinement region that is framed by said DHCBR, wherein said middle layer comprises an epitaxially regrown interface,

wherein said depleting impurity has a maximum concentration that is within 700 Å

of said epitaxially regrown interface, and

wherein said DHCBR forces current flow into said conducting channel during normal operation of said light source.

8. The light source of claim 7, wherein said middle layer comprises a low refractive index mirror layer to either said upper mirror or said lower mirror.

9. The light source of claim 7, wherein said middle layer comprises said cavity spacer layer between at least one of said upper mirror and said lower mirror and said active region.

10. The light source of claim 7, wherein said middle layer comprises AlAs.

11. The light source of claim 7, wherein said cavity spacer layer includes a second impurity region.

12. The light source of claim 7, wherein said active region includes a second impurity region.

13. The light source of claim 7, wherein said depleting impurity region includes silicon or oxygen.

14. The light source of claim 7, further comprising at least one upper cavity spacer layer placed between said DHCBR and said active region, wherein said conducting channel extends into said cavity spacer layer.

15. The light source of claim 7, wherein said middle layer comprises a mesa.

16. The light source of claim 7, wherein said depleting impurity region includes first depleting impurity specie and a second depleting impurity specie.

17. The light source of claim 16, wherein said first depleting impurity comprises a Column II acceptor, wherein said second depleting impurity comprises oxygen.

18. The light source of claim 17, wherein said first depleting impurity comprises beryllium.

19. A semiconductor vertical resonant cavity light source, comprising:

an upper mirror comprising alternating low refractive index mirror layers and high refractive index mirror layers and a lower mirror comprising alternating low refractive index mirror layers and high refractive index mirror layers;

at least one active region for light generation between said upper mirror and said lower mirror;

at least one cavity spacer layer between at least one of said upper mirror and said lower mirror and said active region;

said light source including an inner mode confinement region and an outer current blocking region;

a depleted heterojunction current blocking region (DHCBR) including a depleting impurity region comprising a first depleting impurity specie comprising a Column II acceptor and a second depleting impurity comprising oxygen within said outer current blocking region of at least one of said upper mirror, said lower mirror, and said active region, and

a middle layer including a conducting channel within said inner mode confinement region that is framed by said DHCBR,

wherein said DHCBR forces current flow into said conducting channel during normal operation of said light source.