Charge pump having level-shifting mechanism

• US 10,483,845 B2
• Filed: 09/20/2018
• Issued: 11/19/2019
• Est. Priority Date: 12/26/2017
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Hsueh, Yu-Li, Shen, Chih-Hsien, Hung, Chao-Ching, Huang, Po-Chun
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US16/137,534
• Publication Number:
  US 20190199207A1
• Time in Patent Office: 425 Days
• Field of Search: 327157
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.

Claims

1. A charge pump, comprising:

a pull-up circuit, for selectively providing charges to an output terminal of the charge pump, wherein the pull-up circuit comprises;

a first transistor;

a first capacitor, coupled to one electrode of the first transistor; and

a switched-capacitor circuit, coupled between a supply voltage and another electrode of the first transistor, for boosting a voltage of the other electrode of the first transistor to charge the first capacitor via the first transistor, then the first capacitor and the output terminal of the charge pump are under a charge distribution operation;

wherein when the first capacitor and the output terminal of the charge pump are under the charge distribution operation, the first capacitor is electrically disconnected from the supply voltage.

2. A charge pump, comprising:

a pull-up circuit, for selectively providing charges to an output terminal of the charge pump, wherein the pull-up circuit comprises;

a first transistor;

a first capacitor, coupled to one electrode of the first transistor; and

a switched-capacitor circuit, coupled between a supply voltage and another electrode of the first transistor, for boosting a voltage of the other electrode of the first transistor to charge the first capacitor via the first transistor, then the first capacitor and the output terminal of the charge pump are under a charge distribution operation;

wherein the first transistor is a P-type transistor, and the switched-capacitor circuit comprises;

a second capacitor, wherein a first node of the second capacitor is coupled to a first clock signal;

a first switch, coupled between the supply voltage and a second node of the second capacitor, wherein the first switch is controlled by a second clock signal to connect or disconnect the supply voltage to the second node of the second capacitor, wherein phases of the second clock signal and the first clock signal are inverted; and

a second switch, coupled between the second node of the second capacitor and a source electrode of the first transistor, wherein the second switch is controlled by the first clock signal to connect or disconnect the second capacitor to the source electrode of the first transistor.

3. The charge pump of claim 2, further comprising:

a third switch, coupled between a drain electrode of the first transistor and the output terminal of the charge pump, wherein the third switch is controlled by the second clock signal to connect or disconnect the drain electrode of the first transistor to the output terminal of the charge pump.

4. A charge pump, comprising:

a pull-up circuit, for selectively providing charges to an output terminal of the charge pump, wherein the pull-up circuit comprises;

a first transistor;

a first capacitor, coupled to one electrode of the first transistor; and

a switched-capacitor circuit, coupled between a supply voltage and another electrode of the first transistor, for boosting a voltage of the other electrode of the first transistor to charge the first capacitor via the first transistor, then the first capacitor and the output terminal of the charge pump are under a charge distribution operation;

wherein the pull-up circuit further comprises;

a second transistor, wherein a gate electrode of the second transistor is coupled to a gate electrode of the first transistor, and a first electrode of the second transistor is coupled to the supply voltage; and

a resistor, coupled between a second electrode of the second transistor and a ground voltage, and the second electrode of the second transistor is also coupled to its gate electrode.

5. The charge pump of claim 4, wherein the first transistor and the second transistor are P-type transistors, and the second transistor is barely off when the switched-capacitor circuit boosts the voltage of the other electrode of the first transistor to charge the first capacitor via the first transistor.

6. A charge pump, comprising:

a pull-up circuit, for selectively providing charges to an output terminal of the charge pump, wherein the pull-up circuit comprises;

a first transistor;

a first capacitor, coupled to one electrode of the first transistor; and

a switched-capacitor circuit, coupled between a supply voltage and another electrode of the first transistor, for boosting a voltage of the other electrode of the first transistor to charge the first capacitor via the first transistor, then the first capacitor and the output terminal of the charge pump are under a charge distribution operation;

a pull-down circuit, comprising;

a current source, coupled to the output terminal of the charge pump via a switch, for selectively discharging the output terminal of the charge pump;

wherein the pull-down circuit further comprises;

a third capacitor, wherein a first node of the third capacitor is coupled to a first clock signal, and a second node of the third capacitor is coupled to the current source;

wherein the switch is controlled by a second clock signal to connect or disconnect the current source to the output terminal of the charge pump, and the phases of the second clock signal and the first clock signal are inverted.

7. A phase-locked loop, comprising:

a phase detector, for receiving an input signal and a feedback signal to generate a detection result;

a charge pump, for generating a control signal according to the detection result, wherein the charge pump comprises;

a pull-up circuit, for selectively providing charges to an output terminal of the charge pump, wherein the pull-up circuit comprises;

a first transistor;

a first capacitor, coupled to one electrode of the first transistor; and

a switched-capacitor circuit, coupled between a supply voltage another electrode of the first transistor, for boosting a voltage of the other electrode of the first transistor to charge the first capacitor via the first transistor, then the first capacitor and the output terminal of the charge pump are under a charge distribution operation;

wherein when the first capacitor and the output terminal of the charge pump are under the charge distribution operation, the first capacitor is electrically disconnected from the supply voltage; and

a voltage-controlled oscillator, for generating an output clock signal according to the control signal; and

a frequency divider, for frequency-dividing the output clock signal to generate the feedback signal.

8. The phase-locked loop of claim 7, wherein the first transistor is a P-type transistor, and the switched-capacitor circuit comprises:

a second capacitor, wherein a first node of the second capacitor is coupled to a first clock signal;

a first switch, coupled between the supply voltage and a second node of the second capacitor, wherein the first switch is controlled by a second clock signal to connect or disconnect the supply voltage to the second node of the second capacitor, wherein phases of the second clock signal and the first clock signal are inverted; and

a second switch, coupled between the second node of the second capacitor and a source electrode of the first transistor, wherein the second switch is controlled by the first clock signal to connect or disconnect the second capacitor to the source electrode of the first transistor.

9. The phase-locked loop of claim 8, further comprising:

a third switch, coupled between a drain electrode of the first transistor and the output terminal of the charge pump, wherein the third switch is controlled by the second clock signal to connect or disconnect the drain electrode of the first transistor to the output terminal of the charge pump.

10. The phase-locked loop of claim 7, wherein the pull-up circuit further comprises:

a second transistor, wherein a gate electrode of the second transistor is coupled to a gate electrode of the first transistor, and a first electrode of the second transistor is coupled to the supply voltage; and

a resistor, coupled between a second electrode of the second transistor and a ground voltage, and the second electrode of the second transistor is also coupled to its gate electrode.

11. The phase-locked loop of claim 10, wherein the first transistor and the second transistor are P-type transistors, and the second transistor is barely off when the switched-capacitor circuit boosts the voltage of the other electrode of the first transistor to charge the first capacitor via the first transistor.

12. The phase-locked loop of claim 7, further comprising:

a pull-down circuit, comprising;

a current source, coupled to the output terminal of the charge pump via a switch, for selectively discharging the output terminal of the charge pump.

13. The phase-locked loop of claim 12, wherein the pull-down circuit further comprises:

a third capacitor, wherein a first node of the third capacitor is coupled to a first clock signal, and a second node of the third capacitor is coupled to the current source;

wherein the switch is controlled by a second clock signal to connect or disconnect the current source to the output terminal of the charge pump, and the phases of the second clock signal and the first clock signal are inverted.

14. A charge pump, comprising:

a pull-up circuit, for selectively providing charges to an output terminal of the charge pump, wherein the pull-up circuit comprises;

a first transistor;

a first capacitor, coupled to a first electrode of the first transistor; and

a switched-capacitor circuit, coupled between a supply voltage and a second electrode of the transistor,

a switch, coupled between the first electrode of the first transistor and the output terminal of the charge pump;

wherein when the pull-up circuit operates in a first phase, the switched-capacitor circuit is controlled to charge the first capacitor via the first transistor, and the switch is controlled to disconnect the first electrode of the first transistor from the output terminal of the charge pump; and

when the pull-up circuit operates in a second phase, the switched-capacitor circuit is controlled to be disconnected from the second electrode of the first transistor, and the switch is controlled to connect the first electrode of the first transistor to the output terminal of the charge pump.

15. The charge pump of claim 14, wherein the switch is a third switch, the first transistor is a P-type transistor, and the switched-capacitor circuit comprises:

a second capacitor, wherein a first node of the second capacitor is coupled to a first clock signal;

a first switch, coupled between the supply voltage and a second node of the second capacitor, wherein the first switch is controlled by a second clock signal to connect or disconnect the supply voltage to the second node of the second capacitor, wherein phases of the second clock signal and the first clock signal are inverted; and

a second switch, coupled between the second node of the second capacitor and a source electrode of the first transistor, wherein the second switch is controlled by the first clock signal to connect or disconnect the second capacitor to the source electrode of the first transistor.

16. The charge pump of claim 15, wherein the third switch is controlled by the second clock signal to connect or disconnect the drain electrode of the first transistor to the output terminal of the charge pump.