Phase interpolator, timing generator, and semiconductor integrated circuit

• US 10,483,956 B2
• Filed: 07/19/2018
• Issued: 11/19/2019
• Est. Priority Date: 07/20/2017
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Tsuji, Masanobu
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US16/039,921
• Publication Number:
  US 20190028093A1
• Time in Patent Office: 488 Days
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/156 Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0998 using phase interpolation

Abstract

During a period in which a first signal S₁ and second signal S₂ are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal S_OUT that changes level when the capacitor voltage crosses a predetermined threshold value V_TH. Each circuit unit includes a resistor R_g and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S₁ is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S₂ is the second level and the corresponding bit of the input code is a second value.

Claims

1. A semiconductor integrated circuit comprising:

a set signal generator structured to generate a set signal; and

a reset signal generator structured to generate a reset signal,

wherein at least one from among the set signal generator and the reset signal generator comprises a timing generator, the timing generator comprising N (N≥

2) stages,

wherein an i-th (1≤

i≤

N−

1) stage comprises a first phase interpolator and a second phase interpolator,

wherein an output node of the first phase interpolator in the i-th (1≤

i≤

N−

1) stage is coupled to a first input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,

wherein an output node of the second phase interpolator in the i-th stage is coupled to a second input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,

wherein the first phase interpolator and the second phase interpolator are each arranged such that a first signal is received via the first input node and such that a second signal is received via the second input node, and structured to generate an output signal having an edge at a timing that corresponds to control data,

and wherein the first phase interpolator and the second phase interpolator each comprise a phase interpolator, the phase interpolator comprising;

a first input node coupled to receive a first signal that transits from a first level to a second level;

a second input node coupled to receive a second signal that transits from the first level to the second level with a delay with respect to the first signal;

a first line coupled to receive a first voltage;

a second line coupled to receive a second voltage;

an intermediate line;

a capacitor having one end coupled to the intermediate line;

an initializing circuit structured to initialize a voltage across the capacitor during a period in which the first signal and the second signal are both set to the first level;

a plurality of circuit units that correspond to a plurality of bits of an input code, and coupled in parallel between the intermediate line and the second line; and

an output circuit structured to generate an output signal having a level that changes when the voltage across the capacitor crosses a predetermined threshold value,

wherein each circuit unit comprises;

a resistor and a first path arranged in series between the intermediate line and the second line; and

a second path arranged in parallel with the first path,

wherein the first path is structured such that, when the first signal is set to the second level and the corresponding bit of the input code is set to a first value, the first path is turned on,

wherein the second path is structured such that, when the second signal is set to the second level and the corresponding bit of the input code is set to a second value, the second path is turned on,

and wherein the semiconductor integrated circuit is structured to output a pulse signal that transits to a first level according to an output signal of the set signal generator, and that transits to a second level according to an output signal of the reset signal generator.

2. A semiconductor integrated circuit comprising:

a set signal generator structured to generate a set signal; and

a reset signal generator structured to generate a reset signal,

wherein at least one from among the set signal generator and the reset signal generator comprises a timing generator, the timing generator comprising N (N≥

2) stages,

wherein an i-th (1≤

i≤

N−

1) stage comprises a first phase interpolator and a second phase interpolator,

wherein an output node of the first phase interpolator in the i-th (1≤

i≤

N−

1) stage is coupled to a first input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,

wherein an output node of the second phase interpolator in the i-th stage is coupled to a second input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,

wherein the first phase interpolator and the second phase interpolator are each arranged such that a first signal is received via the first input node and such that a second signal is received via the second input node, and structured to generate an output signal having an edge at a timing that corresponds to control data,

and wherein the semiconductor integrated circuit is structured to output a pulse signal that transits to a first level according to an output signal of the set signal generator, and that transits to a second level according to an output signal of the reset signal generator.

3. The semiconductor integrated circuit according to claim 2, wherein the pulse signal is configured as a pulse width modulation signal.

4. The semiconductor integrated circuit according to claim 2, configured as a controller for a class D amplifier.

5. The semiconductor integrated circuit according to claim 2, configured as a controller for a DC/DC converter.

6. The semiconductor integrated circuit according to claim 2, configured as a controller for an LED driver.

7. The semiconductor integrated circuit according to claim 2, configured as a controller for a motor.

8. The semiconductor integrated circuit according to claim 2, wherein, in the i-th (1≤

i≤

N−

1) stage, there is a time difference between edges of output signals of the first phase interpolator and the second phase interpolator that corresponds to a time resolution provided by the stage.

9. The semiconductor integrated circuit according to claim 2, wherein, in the first stage, a common first reference signal is input to each of the first input nodes of the first phase interpolator and the second phase interpolator, and a common second reference signal is input to each of the second input nodes of the first phase interpolator and the second phase interpolator.

10. The semiconductor integrated circuit according to claim 2, wherein, in the first stage, a common signal is input to each of the second input node of the first phase interpolator and the first input node of the second phase interpolator.

11. The semiconductor integrated circuit according to claim 2, wherein the first phase interpolator and the second phase interpolator each comprise:

a capacitor;

a charging/discharging circuit structured (i) to charge or otherwise discharge the capacitor with an amount of current that corresponds to the control data according to the first signal, and (ii) to charge or otherwise discharge the capacitor with a constant amount of current according to the second signal; and

an output circuit structured to generate the output signal having a level that changes when a voltage across the capacitor reaches a threshold value.