Transceiver for communication and method for controlling communication

• US 10,484,103 B2
• Filed: 04/23/2019
• Issued: 11/19/2019
• Est. Priority Date: 03/14/2016
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Tomita, Kazuhiro, Inui, Masuo
• Primary Examiner(s): Aghdam, Freshteh N
• Application Number:
  US16/392,405
• Publication Number:
  US 20190327005A1
• Time in Patent Office: 210 Days
• CPC Class Codes: H04B 1/3822 specially adapted for use in vehicles H04B1/3827 takes precedence
• CPC Class Codes: H04B 15/005 Reducing noise, e.g. humm, from the supply
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4906 using binary codes
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Claims

1. A clock extension peripheral interface (CXPI) communication system, comprising:

a master circuit including a first transceiver, wherein the first transceiver is configured to generate a signal by modulating a timing signal;

a communication bus; and

a slave circuit including a second transceiver, wherein the second transceiver further includes;

a first timing module configured to determine a first time based on a timing at which the signal received through the communication bus from the master circuit is detected to have started rising from a low level to a high level;

a timing adjustment module configured to determine a second time based on the first time and a predetermined time difference value; and

an encoder configured to extend a length of time of a combined signal on the communication bus is at the low level by pulling a data signal to be output to the master circuit through the communication bus from the high level to the low level at the second time.

2. The CXPI communication system of claim 1, wherein the timing adjustment module computes the predetermined time difference value based on a frequency at which a harmonic level is reduced and a natural number.

3. The CXPI communication system of claim 1, wherein the second time is generated by subtracting the predetermined time difference value from the first time.

4. The CXPI communication system of claim 1, wherein the slave circuit further comprises:

a second timing module configured to determine a third time based on a timing at which the signal received through the communication bus from the master circuit is detected to have started falling from the high level to the low level.

5. The CXPI communication system of claim 4, wherein the second time is later than the third time and earlier than the first time.

6. The CXPI communication system of claim 1, wherein the slave circuit further comprises a clock rise detector configured to detect a rising edge of the signal received through the communication bus from the master circuit.

7. The CXPI communication system of claim 4, wherein the slave circuit further comprises:

a first comparator configured to generate a first result based on a voltage level of the signal received through the communication bus from the master circuit and a first reference voltage; and

a second comparator configured to generate a second result based on the voltage level of the signal received through the communication bus from the master circuit and a second reference voltage, wherein the high level is greater than the first reference voltage, the first reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the low level.

8. The CXPI communication system of claim 7, wherein the first and second timing modules, based on the first and second results, respectively determine the first time and the third time.

9. The CXPI communication system of claim 1, wherein the signal is a Pulse Width Modulation (PWM) signal.

10. The CXPI communication system of claim 1 is disposed in an automobile electronic control system.

11. A method of operating a clock extension peripheral interface (CXPI) communication system, comprising:

generating a signal by modulating a timing signal from a master circuit of the CXPI communication system;

transmitting the signal to a slave circuit through a communication bus;

detecting a change from a low level to a high level of the signal;

generating a second time based on a first time and a predetermined time difference value, wherein the signal is detected to be changing from the low level to the high level at the first time; and

extending the low level of a combined signal on the communication bus by pulling a data signal to be output, from the slave circuit to the master circuit, on the communication bus from the high level to the low level, wherein the data signal is pulled to the low level at the second time.

12. The method of claim 11, wherein the predetermined time difference is computed based on a frequency at which a harmonic level is reduced and a natural number.

13. The method of claim 11, wherein generating the second time further comprising:

computing the second time by subtracting the predetermined time difference from the first time.

14. The method of claim 11, further comprising:

generating a third time based on a timing at which the signal received through the communication bus from the master circuit is detected to have started falling from the high level to the low level.

15. The method of claim 14, wherein the second time is later than the third time and earlier than the first time.

16. The method of claim 11, further comprising:

detecting a rising edge of the signal received through the communication bus, by a clock rise detector.

17. The method of claim 14, further comprising:

generating a first result, by a first comparator, based on a voltage level of the signal received through the communication bus from the master circuit and a first reference voltage; and

generating a second result, by a second comparator, based on the voltage level of the signal received through the communication bus from the master circuit and a second reference voltage, wherein the high level is greater than the first reference voltage, the first reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the low level.

18. The method of claim 17, further comprising:

determining the first and third times based on the first and second results.

19. The method of claim 11, wherein the signal is a Pulse Width Modulation (PWM) signal.

20. The method of claim 11, wherein the master and slave circuits are disposed in an automobile electronic control system.