Transceiver for communication and method for controlling communication
First Claim
1. A clock extension peripheral interface (CXPI) communication system, comprising:
- a master circuit including a first transceiver, wherein the first transceiver is configured to generate a signal by modulating a timing signal;
a communication bus; and
a slave circuit including a second transceiver, wherein the second transceiver further includes;
a first timing module configured to determine a first time based on a timing at which the signal received through the communication bus from the master circuit is detected to have started rising from a low level to a high level;
a timing adjustment module configured to determine a second time based on the first time and a predetermined time difference value; and
an encoder configured to extend a length of time of a combined signal on the communication bus is at the low level by pulling a data signal to be output to the master circuit through the communication bus from the high level to the low level at the second time.
3 Assignments
0 Petitions
Accused Products
Abstract
An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.
-
Citations
20 Claims
-
1. A clock extension peripheral interface (CXPI) communication system, comprising:
-
a master circuit including a first transceiver, wherein the first transceiver is configured to generate a signal by modulating a timing signal; a communication bus; and a slave circuit including a second transceiver, wherein the second transceiver further includes; a first timing module configured to determine a first time based on a timing at which the signal received through the communication bus from the master circuit is detected to have started rising from a low level to a high level; a timing adjustment module configured to determine a second time based on the first time and a predetermined time difference value; and an encoder configured to extend a length of time of a combined signal on the communication bus is at the low level by pulling a data signal to be output to the master circuit through the communication bus from the high level to the low level at the second time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method of operating a clock extension peripheral interface (CXPI) communication system, comprising:
-
generating a signal by modulating a timing signal from a master circuit of the CXPI communication system; transmitting the signal to a slave circuit through a communication bus; detecting a change from a low level to a high level of the signal; generating a second time based on a first time and a predetermined time difference value, wherein the signal is detected to be changing from the low level to the high level at the first time; and extending the low level of a combined signal on the communication bus by pulling a data signal to be output, from the slave circuit to the master circuit, on the communication bus from the high level to the low level, wherein the data signal is pulled to the low level at the second time. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification