Network functions virtualization platforms with function chaining capabilities

• US 10,489,178 B2
• Filed: 04/28/2015
• Issued: 11/26/2019
• Est. Priority Date: 04/28/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rabi, Abdel Hafiz, Chen, Allen, Lewis, Mark Jonathan, Zhang, Jiefan
• Primary Examiner(s): Sun, Scott C
• Application Number:
  US14/698,636
• Publication Number:
  US 20160321094A1
• Time in Patent Office: 1,673 Days
• Field of Search: None
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2009/45595 Network integration; Enabling network access in virtual machine instances
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G06F 2213/28 DMA
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

Claims

1. An integrated circuit die in a network functions virtualization (NFV) platform, comprising:

a first virtual function hardware accelerator module n the integrated circuit die that performs a first function;

a second virtual function hardware accelerator module in the integrated circuit die that performs a second function; and

data switching circuitry in the integrated circuit die that receives data output from the first virtual function hardware accelerator module, that checks the data output from the first virtual function hardware accelerator module to determine whether the data satisfies an accelerator condition associated with the second virtual function hardware accelerator, and that routes the data output from the first virtual function hardware accelerator module directly back to the second virtual function hardware accelerator module in response to determining that the data satisfies the accelerator condition.

2. The integrated circuit die defined in claim 1, wherein the second function that is performed by the second virtual function hardware accelerator module is different than the first function that is performed by the first virtual function hardware accelerator module.

3. The integrated circuit die defined in claim 1, further comprising:

a third virtual function hardware accelerator module in the integrated circuit die that performs a third function, wherein the data switching circuitry receives data output from the second virtual function hardware accelerator module and routes that data directly back to the third virtual function hardware accelerator module.

4. The integrated circuit die defined in claim 1, further comprising:

a direct memory access (DMA) engine that receives the data from an off-chip memory device.

5. The integrated circuit die defined in claim 1, wherein the data that is output from the second virtual function hardware accelerator module is fed back to a selected virtual machine in a plurality of virtual machines running on an external host processor that is coupled to the integrated circuit die and that runs a hypervisor.

6. The integrated circuit die defined in claim 5, further comprising:

programmable logic elements that can be reconfigured to Perform different custom function.

7. The integrated circuit die defined in claim 5, wherein the data switching circuitry is configured to performing function chaining according to a set of predetermined chaining instructions without sending intermediate data back to the external host processor.

8. The integrated circuit die defined in claim 1, wherein the first function is performed in response to an additional accelerator condition being satisfied.

9. The integrated circuit die defined in claim 8, wherein the first function is skipped when the additional accelerator condition has not been satisfied.

10. The integrated circuit die defined in claim 8, wherein the acceleration condition is different than the additional accelerator condition.

11. The integrated circuit die defined in claim 8, wherein the data switching circuitry is further configured to analyze sideband signals associated with the data to determine whether the second function should be performed on the data.

12. An integrated circuit, comprising:

a first virtual function hardware accelerator on the integrated circuit

a second virtual function hardware accelerator on the integrated circuit; and

data switching circuitry on the integrated circuit that receives data output from the first virtual function hardware accelerator, that analyzes the data to determine whether the data needs to be chained at the second virtual function hardware accelerator, that routes the data directly to the second virtual function hardware accelerator in response to determining that the data needs to be chained, and that routes the data directly to an external host in response to determining that the data does not need to be chained.

13. The integrated circuit of claim 12, wherein the first virtual function hardware accelerator performs a first function, and wherein the second virtual function hardware acceleration performs a second function that is different than the first function.

14. The integrated circuit of claim 12, wherein the data that is output from the second virtual function hardware accelerator is fed back to a selected virtual machine in a plurality of virtual machines running on an external host processor that is coupled to the integrated circuit and that runs a hypervisor.

15. The integrated circuit of claim 12, wherein the data is routed from the first virtual function hardware accelerator through the data switching circuitry to the second virtual function hardware accelerator.