Quality of cache management in a computer

• US 10,489,296 B2
• Filed: 09/22/2016
• Issued: 11/26/2019
• Est. Priority Date: 09/22/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gellerich, Wolfgang, Held, Peter M., Koch, Gerrit, Raisch, Christoph, Schwidefsky, Martin
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US15/272,459
• Publication Number:
  US 20180081813A1
• Time in Patent Office: 1,160 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

Embodiments here relate to managing a cache by exploiting a cache line hierarchy is provided. Managing the cache includes reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch. Further, managing the cache includes prefetching and restoring cache lines of the first task to the cache based on the cache references. Note that the cache lines can be predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.

Claims

1. A computer program product, the computer program product comprising a computer readable storage medium having program instructions managing a cache by exploiting a cache line hierarchy embodied therewith, the program instructions executable by a processor to cause the processor to perform:

reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch;

extracting cache references of a second task by reading cache references of the second task from a cache reference save area of a second data structure; and

asynchronously prefetching by executing a prefetch instruction definition to exploit the cache line hierarchy, the asynchronously prefetching comprising restoring hot cache lines, as cache lines of the first task, to the cache to replace cold cache lines based on the cache references, the prefetch instruction definition comprising a code defining the prefetch instruction definition for prefetching, a first field specifying a register with an identification of data items related to the first task, a base field designating a base register, and a displacement field designating a displacement,

wherein the cache lines were predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.

2. The computer program product of claim 1, wherein the extracting by the processor includes executing an extract instruction definition comprising a code defining the extract instruction definition for prefetching, a first field specifying a register with an identification of data items related to the second task, a base field designating a base register, and a displacement field designating a displacement.

3. The computer program product of claim 1, wherein the prefetching is performed after the context switch and before an execution of first task.

4. The computer program product of claim 1, wherein the base register forms an address of a memory location within a register save area of the data structure of the first task.

5. The computer program product of claim 1, wherein the context switch comprises changing from an execution of the second task to an execution of the first task.

6. A system, comprising a processor and a memory storing program instructions managing a cache by exploiting a cache line hierarchy thereon, the program instructions executable by a processor to cause the system to perform:

reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch;

extracting cache references of a second task by reading cache references of the second task from a cache reference save area of a second data structure; and

asynchronously prefetching by executing a prefetch instruction definition to exploit the cache line hierarchy, the asynchronously prefetching comprising restoring hot cache lines, as cache lines of the first task, to the cache to replace cold cache lines based on the cache references, the prefetch instruction definition comprising a code defining the prefetch instruction definition for prefetching, a first field specifying a register with an identification of data items related to the first task, a base field designating a base register, and a displacement field designating a displacement,

wherein the cache lines were predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.

7. The system of claim 6, wherein the prefetching is performed after the context switch and before an execution of first task.