Flash storage failure rate reduction and hyperscale infrastructure robustness enhancement through the MRAM-NOR flash based cache architecture

• US 10,489,313 B2
• Filed: 10/31/2016
• Issued: 11/26/2019
• Est. Priority Date: 10/31/2016
• Status: Active Grant

• Current Assignee: Alibaba Group Holding Ltd.
• Original Assignee: Alibaba Group Holding Ltd.
• Inventors: Li, Shu
• Primary Examiner(s): Li, Zhuo H
• Application Number:
  US15/338,897
• Publication Number:
  US 20180121109A1
• Time in Patent Office: 1,121 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the present invention provide flash-based storage with non-volatile memory components. MRAM is mainly used as a data buffer, and NOR flash is used to store metadata, such as FTL information, thereby providing non-volatile storage and significantly simplifying power failure mitigation. MRAM and NOR are jointly used to share the work performed by DRAM in existing SSDs based on the characteristics of the data stored, reducing the power consumption and cost of the SSD. The cache fault rate is reduced because both MRAM and NOR are immune from soft errors. Moreover, the working mechanisms are simplified and the power-up duration is significantly reduced because less data is copied from NAND flash, as there is no need to move all of the FTL information back to NAND flash at power off.

Claims

1. A flash storage device, comprising:

a NAND flash memory;

a NOR flash memory that stores a first type of data that includes a flash translation layer that maps logical block addresses to physical block addresses;

a MRAM memory that stores a second type of data; and

a memory controller coupled to the NAND flash memory, the NOR flash memory, and the MRAM memory, the memory controller to;

receive a host write request that includes a received logical block address and a block of data;

store the received logical block address and the block of data in the MRAM memory;

access the flash translation layer in the NOR flash memory to determine a translated physical block address for the block of data from the received logical block address; and

write the block of data stored in the MRAM memory to the translated physical block address in the NAND flash memory.

2. The flash storage device of claim 1, wherein:

the MRAM memory stores both the first and second types of data; and

the memory controller to receive a first logical block address with a first write request and a second logical block address with a second write request, and access in parallel the flash translation layer in the MRAM memory and the flash translation layer in the NOR flash memory to determine a first physical block address for the first logical block address from the MRAM memory and a second physical block address for the second logical block address from the NOR flash memory.

3. The flash storage device of claim 2, wherein:

the NOR flash memory includes a flash translation layer unit and a plurality of NOR flash units coupled to the flash translation layer unit; and

the NAND flash memory includes a NAND flash interface and a plurality of NAND flash units coupled to the NAND flash interface.

4. The flash storage device of claim 3, wherein the MRAM memory includes a buffer and a plurality MRAM units coupled to the buffer.

5. A flash storage device, comprising:

a NAND flash memory;

a NOR flash memory that includes a flash translation layer that maps logical block addresses to physical block addresses;

a MRAM memory; and

a memory controller coupled to the NAND flash memory, the NOR flash memory, and the MRAM memory, the memory controller to;

receive a write request that includes a received logical block address and a block of data;

store the received logical block address and the block of data in the MRAM memory;

determine a translated physical block address for the block of data, associate the translated physical block address with the received logical block address, and store the translated physical block address with the received logical block address in the MRAM memory;

write the block of data stored in the MRAM memory to the translated physical block address in the NAND flash memory;

receive a read request from a host to read requested data from a first logical block address;

determine if the first logical block address is stored in the MRAM memory;

read data associated with the first logical block address from the MRAM memory when the first logical block address is stored in the MRAM memory, and send the data read from the MRAM memory to the host;

access the flash translation layer in the NOR flash memory to determine a first physical block address that corresponds with the first logical block address when the first logical block address is not stored in the MRAM memory; and

read data associated with the first physical block address from the NAND flash memory, and send the data read from the NAND flash memory to the host.

6. The flash storage device of claim 5, wherein the memory controller to further backup data stored in the MRAM memory in the NOR flash memory.

7. The flash storage device of claim 5, wherein the memory controller to further backup data stored in the NOR flash memory in the MRAM memory.

8. The flash storage device of claim 5, wherein the memory controller to further write the received logical block address and the translated physical block address that is associated with the received logical block address and stored in the MRAM memory to the NOR flash memory to update the flash translation layer.

9. A non-transitory computer-readable medium having computer-readable instructions stored thereon to be executed by a computer, the instructions including a method comprising:

receiving a host write request that includes a received logical block address and a block of data;

storing the received logical block address and the block of data in a MRAM memory;

accessing a flash translation layer in a NOR flash memory to determine a translated physical block address for the block of data from the received logical block address; and

writing the block of data stored in the MRAM memory to the translated physical block address in a NAND flash memory.

10. The medium of claim 9 wherein the method further comprises:

writing the received logical block address and the translated physical block address that is associated with the received logical block address and stored in the MRAM memory to the NOR flash memory to update the flash translation layer in the NOR flash memory; and

receiving a first logical block address with a first write request and a second logical block address with a second write request, and accessing in parallel a flash translation layer in the MRAM memory and the flash translation layer in the NOR flash memory to determine a first physical block address for the first logical block address from the MRAM memory and a second physical block address for the second logical block address from the NOR flash memory.

11. A non-transitory computer-readable medium having computer-readable instructions stored thereon to be executed by a computer, the instructions including a method comprising:

receiving a write request that includes a received logical block address and a block of data;

storing the received logical block address and the block of data in a MRAM memory;

determining a translated physical block address for the block of data, associating the translated physical block address with the received logical block address, and storing the translated physical block address with the received logical block address in the MRAM memory;

writing the block of data stored in the MRAM memory to the new translated physical block address in a NAND flash memory;

receiving a read request from a host to read requested data from a first logical block address;

determining if the first logical block address is stored in the MRAM memory;

reading data associated with the first logical block address from the MRAM memory when the first logical block address is stored in the MRAM memory, and sending the data read from the MRAM memory to the host;

accessing a flash translation layer in a NOR flash memory to determine a first physical block address that corresponds with the first logical block address when the first logical block address is not stored in the MRAM memory; and

reading data associated with the first physical block address from the NAND flash memory, and sending the data read from the NAND flash memory to the host.

12. The medium of claim 11 wherein the method further comprises backing up data stored in the MRAM memory in the NOR flash memory.

13. The medium of claim 11 wherein the method further comprises backing up data stored in the NOR flash memory in the MRAM memory.

14. The medium of claim 11 wherein the method further comprises verifying data written to the NOR flash memory and the NAND flash memory.

15. A method of writing data to a flash storage device, the method comprising:

receiving a host write request that includes a received logical block address and a block of data;

storing the received logical block address and the block of data in a MRAM memory;

accessing a flash translation layer in a NOR flash memory to determine a translated physical block address for the block of data from the received logical block address; and

writing the block of data stored in the MRAM memory to the translated physical block address in a NAND flash memory.

16. The method of claim 15, further comprising receiving a first logical block address with a first write request and a second logical block address with a second write request, and accessing in parallel a flash translation layer in the MRAM memory and the flash translation layer in the NOR flash memory to determine a first physical block address for the first logical block address from the MRAM memory and a second physical block address for the second logical block address from the NOR flash memory.

17. The method of claim 16, further comprising:

writing the received logical block address and the translated physical block address that is associated with the received logical block address and stored in the MRAM memory to the NOR flash memory to update the flash translation layer in the NOR flash memory; and

verifying data written to the NOR flash memory and the NAND flash memory.

18. The method of claim 16, further comprising backing up data stored in the MRAM memory in the NOR flash memory.

19. The method of claim 16, further comprising backing up data stored in the NOR flash memory in the MRAM memory.

20. A method of writing data to a flash storage device, the method comprising:

receiving a write request that includes a received logical block address and a block of data;

storing the received logical block address and the block of data in a MRAM memory;

determining a translated physical block address for the block of data, associating the translated physical block address with the received logical block address, and storing the translated physical block address with the received logical block address in the MRAM memory;

writing the block of data stored in the MRAM memory to the translated physical block address in a NAND flash memory;

receiving a read request from a host to read requested data from a first logical block address;

determining if the first logical block address is stored in the MRAM memory;

reading data associated with the first logical block address from the MRAM memory when the first logical block address is stored in the MRAM memory, and sending the data read from the MRAM memory to the host;

accessing a flash translation layer in a NOR flash memory to determine a first physical block address that corresponds with the first logical block address when the first logical block address is not stored in the MRAM memory; and

reading data associated with the first physical block address from the NAND flash memory, and sending the data read from the NAND flash memory to the host.