Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave

• US 10,489,323 B2
• Filed: 12/20/2016
• Issued: 11/26/2019
• Est. Priority Date: 12/20/2016
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Geng, Guanghui, Tune, Andrew David, Sara, Daniel Adam, Mannava, Phanindra Kumar, Mathewson, Bruce James, Jalal, Jamshed
• Primary Examiner(s): Sun, Scott C
• Application Number:
  US15/384,688
• Publication Number:
  US 20180173660A1
• Time in Patent Office: 1,071 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

Claims

1. A data processing system comprising:

a master node to initiate data transmissions;

one or more slave nodes to receive the data transmissions; and

a home node to control coherency amongst data stored by the data processing system;

in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node;

wherein;

the master node is configured to issue a transmission request, requesting a data transmission, the data transmission being to one of the one or more slave nodes, to the home node;

the home node is configured to serialise transmission requests and access requests to the one or more slave nodes so that data written to a memory address at a slave node is consistent with data read from that memory address in response to a subsequent access request; and

the home node is configured, in response to serialisation of a given transmission request requesting a data transmission to a given slave node of the one or more slave nodes, to issue an authorisation indicating that the data transmission corresponding to the given transmission request should be made directly to the given slave node.

2. A system according to claim 1, in which:

the authorisation issued by the home node includes a source node identifier and a target node identifier; and

the source node identifier indicates that the given slave node was the source of the authorisation.

3. A system according to claim 2, in which the data transmission includes a target node identifier derived from the source node identifier of the authorisation issued by the home node.

4. A system according to claim 1, in which the home node is configured to inhibit a second data transmission relating to a later-serialised transmission request from writing data to the same memory address as a first data transmission relating to an earlier-serialised transmission request, until after completion of the first data transmission.

5. A system according to claim 1, in which each of the one or more slave nodes is configured to accept each data transmission directed to that slave node independently of any other data transmissions directed to that slave node.

6. A system according to claim 1, comprising:

interface circuitry between the master node and the home and the one or more slave nodes;

the interface circuitry being configured to receive a transmission request and a data transmission from the master node according to a first data transfer protocol and to transfer data from the received data transmission to the given slave node according to a second, different, data transfer protocol.

7. A system according to claim 6, in which the interface circuitry is configured to generate a transmission message, for transmission to the given slave node, the transmission message including at least memory address information from the received transmission request and data from the received data transmission.

8. A system according to claim 7, in which the interface circuitry comprises a buffer to buffer at least one of:

address information from the received transmission request; and

data from the received data transmission.

9. A system according to claim 6, in which the master node has an associated cache memory and at least one of the one or more slave nodes provides a higher level memory;

the system comprising at least one further master node;

in which, in response to a data access request from the further master node to retrieve data from a memory address stored in the cache memory, the interface circuitry is configured to receive data retrieved from the cache memory and to provide the retrieved data to the further master node.

10. A system according to claim 9, in which, if the retrieved data in the cache memory is detected to be different to data held at the same memory address in the higher level memory, the interface circuitry is configured to transmit the retrieved data as a data transmission to the higher level memory.

11. A system according to claim 1, in which, in respect of a data transmission from the master node to the one of the slave nodes, the slave node is configured to issue a credit for the data transfer, the credit being provided to the master node by a path which bypasses the home node.

12. A system according to claim 11, in which the slave node is configured to issue a single message comprising the credit and an acknowledgement.

13. A system according to claim 1, in which one or more of the slave nodes are configured to operate according a different communication protocol to the master node.

14. A system according to claim 13, in which the master node is configured to operate according to a Coherent Hub Interface protocol and one or more of the slave nodes are configured to operate according to an Advanced Extensible Interface protocol.

15. A data processing method comprising:

a master node initiating data transmissions to one or more slave nodes;

a home node controlling coherency amongst data stored at the one or more slave nodes;

the master node transmitting data to one of the one or more slave nodes bypassing the home node;

the master node issuing a transmission request, requesting a data transmission, the data transmission being to one of the one or more slave nodes, to the home node;

the home node serialising transmission requests and access requests to the one or more slave nodes so that data written to a memory address at a slave node is consistent with data read from that memory address in response to a subsequent access request; and

the home node, in response to serialisation of a given transmission request requesting a data transmission to a given slave node of the one or more slave nodes, issuing an authorisation indicating that the data transmission corresponding to the given transmission request should be made directly to the given slave node.