Machine learning based post route path delay estimator from synthesis netlist

• US 10,489,542 B2
• Filed: 04/24/2018
• Issued: 11/26/2019
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Ren, Mark, Khailany, Brucek
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US15/960,833
• Publication Number:
  US 20190325092A1
• Time in Patent Office: 581 Days
• Field of Search: 716104
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 3/082 modifying the architecture, e.g. adding, deleting or silencing nodes or connections

Abstract

A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.

Claims

1. A device for generation a circuit fabrication structure, the device comprising:

neural network logic, comprising

an embedding layer to;

receive a gate function vector and an embedding width; and

alter a shape of the gate function vector by the embedding width;

a concatenator to;

receive a gate feature input vector; and

concatenate the gate feature input vector with the gate function vector altered by the embedding width;

a convolution layer to;

receive a window size, stride, and output feature size; and

generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer;

a fully connected layer to reduce the output convolution vector to a final circuit path delay output; and

logic to utilize the final circuit delay output in a circuit fabrication structure.

2. The device of claim 1, the neural network further comprising a dropout layer to:

receive the output convolution vector and a dropout factor;

regularize the output convolution vector based on the dropout factor; and

send the output convolution vector that has been regularized to the fully connected layer.

3. The device of claim 2, wherein the dropout factor is 0.1.

4. The device of claim 2, wherein the embedding layer has the embedding width of 1.

5. The device of claim 1, wherein the convolution layer is a 1D convolution layer.

6. The device of claim 1, wherein the window size is 4, the stride is 1, and the output feature size is 1.

7. The device of claim 1, wherein the convolution layer of the neural network utilizes a rectified linear unit as an activation function.

8. The device of claim 1, wherein the fully connected layer of the neural network utilizes a rectified linear unit as an activation function.

9. The device of claim 1, wherein the fully connected layer of the neural network utilizes a mean square error function as an objective function.

10. The device of claim 1, wherein the gate feature input vector comprises one or more of a gate output fanout, an output Manhattan distance, a gate delay, and a gate output slew.

11. The device of claim 10, further including one or more of a gate logic effort, a gate output capacitance, an average routing congestion estimation, and a maximum routing congestion estimation.

12. The device of claim 1, wherein the gate function vector and the gate feature input vector are determined from a microchip design.

13. The device of claim 12, wherein the gate function vector and the gate feature input vector are collected from placements on a synthesis netlist.

14. The device of claim 1, wherein a size of the gate function vector is determined from a maximum number of gates on a circuit path.

15. The device of claim 14, the gate function vector truncated to the maximum number of gates on the path.

16. The device of claim 14, wherein the maximum number of gates on the path has a value of 51.

17. The device of claim 14, wherein the gate function vector is converted from a string input to an integer input by a categorical encoding method.