Apparatuses and methods for distributing row hammer refresh events across a memory device
First Claim
1. An apparatus comprising:
- a first group of chips and a second group of chips, the first group of chips including a first chip and a second chip, the first chip including a first memory array, the second chip including a second memory array;
wherein one refresh event of first and second refresh events is performed for each chip of the first and second chips, the first refresh event is based, at least in part, on an internal counter signal, and the second refresh event is based, at least in part, on a first refresh command,wherein the first refresh command is supplied in common to the first and second chips of the first group of chips to cause the first chip to perform a first refresh operation for the first refresh event on a plurality of first memory cells in at least one bank of a plurality of first banks in the first memory array and the second chip to perform a second refresh operation for the second refresh event on a plurality of second memory cells in at least one bank of a plurality of second banks in the second memory array,wherein the plurality of first memory cells are different in number than the plurality of second memory cells,wherein each of the first and second refresh events is performed based, at least in part, on a token signal received from an external controller,wherein the first refresh event is performed when the token signal is asserted by the external controller, andwherein the second refresh event is performed when the toke signal is not asserted by the external controller.
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Abstract
Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.
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Citations
10 Claims
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1. An apparatus comprising:
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a first group of chips and a second group of chips, the first group of chips including a first chip and a second chip, the first chip including a first memory array, the second chip including a second memory array; wherein one refresh event of first and second refresh events is performed for each chip of the first and second chips, the first refresh event is based, at least in part, on an internal counter signal, and the second refresh event is based, at least in part, on a first refresh command, wherein the first refresh command is supplied in common to the first and second chips of the first group of chips to cause the first chip to perform a first refresh operation for the first refresh event on a plurality of first memory cells in at least one bank of a plurality of first banks in the first memory array and the second chip to perform a second refresh operation for the second refresh event on a plurality of second memory cells in at least one bank of a plurality of second banks in the second memory array, wherein the plurality of first memory cells are different in number than the plurality of second memory cells, wherein each of the first and second refresh events is performed based, at least in part, on a token signal received from an external controller, wherein the first refresh event is performed when the token signal is asserted by the external controller, and wherein the second refresh event is performed when the toke signal is not asserted by the external controller. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
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a plurality of chips including a first chip having a first memory array, the plurality of chips further including a second chip having a second memory array, wherein one refresh event of first and second refresh events is performed for each chip of the first chip and the second chip, wherein, for the first refresh event, a plurality of first memory cells in at least one bank of a plurality of first banks in the first memory array of the first chip are refreshed based, at least in part, on an internal counter signal, wherein, for the second refresh event, the second chip is configured to perform, based, at least in part, on a refresh command supplied in common to the first and second chips of the plurality of chips, a second refresh operation on a plurality of second memory cells in at least one bank of a plurality of second banks in the second memory array, wherein the plurality of first memory cells are different in number than the plurality of second memory cells, wherein each of the first and second refresh events is performed based, at least in part, on a token signal received from an external controller, wherein the first refresh event is performed when the token signal is asserted by the external controller, and wherein the second refresh event is performed when the toke signal is not asserted by the external controller. - View Dependent Claims (9, 10)
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Specification