Semiconductor system and semiconductor device

• US 10,490,253 B2
• Filed: 09/12/2018
• Issued: 11/26/2019
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Chae, Haengseon
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US16/129,442
• Publication Number:
  US 20190311764A1
• Time in Patent Office: 440 Days
• Field of Search: 365174
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor system may include a controller and a semiconductor device. The controller may be configured to output a command. The semiconductor device may be configured to receive and decode the command and generate an internal command to perform a preset operation. The semiconductor device may be configured to update a synchronization temperature code with a temperature code when the temperature code changes. The semiconductor device may be configured to apply the synchronization temperature code to the controller in synchronization with the internal command.

Claims

1. A semiconductor system comprising:

a controller configured to output a command; and

a semiconductor device configured to receive and decode the command and generate an internal command to perform a preset operation, update a synchronization temperature code with a temperature code when the temperature code changes, and apply the synchronization temperature code to the controller in synchronization with the internal command.

2. The semiconductor system according to claim 1, wherein the preset operation is set as a mode register read operation, and the internal command is set as a mode register read command.

3. The semiconductor system according to claim 1, wherein the temperature code has a logic level combination which corresponds to an internal temperature of the semiconductor device.

4. The semiconductor system according to claim 1, wherein the semiconductor device is further configured to generate a synchronization update flag which is enabled for a period in which the synchronization temperature code is updated, and apply the synchronization update flag to the controller in synchronization with the internal command.

5. The semiconductor system according to claim 4, wherein the semiconductor device comprises:

an update pulse generation circuit configured to generate an update pulse when the temperature code changes.

6. The semiconductor system according to claim 5, wherein the semiconductor device further comprises:

a command latch signal generation circuit configured to generate a command latch signal from the temperature code in response to the internal command;

an update latch signal generation circuit configured to generate an update latch signal from the temperature code in response to the update pulse; and

a temperature code output circuit configured to generate the synchronization temperature code from the command latch signal in response to an output control pulse.

7. The semiconductor system according to claim 6, wherein the command latch signal generation circuit latches the temperature code when the internal command is generated, and outputs the latched temperature code as the command latch signal.

8. The semiconductor system according to claim 6, wherein the update latch signal generation circuit latches the temperature code when the update pulse is generated, and outputs the latched temperature code as the update latch signal.

9. The semiconductor system according to claim 6, wherein the temperature code output circuit outputs the command latch signal as the synchronization temperature code when the output control pulse is generated.

10. The semiconductor system according to claim 6, wherein the semiconductor device further comprises:

an output control pulse generation circuit configured to generate the output control pulse based on a comparison between the command latch signal and the update latch signal.

11. The semiconductor system according to claim 10, wherein the output control pulse generation circuit generates the output control pulse when the command latch signal and the update latch signal are the same.

12. The semiconductor system according to claim 6, wherein the semiconductor device further comprises:

an update flag generation circuit configured to generate an update flag in response to the update pulse, the synchronization temperature code, and the temperature code.

13. The semiconductor system according to claim 12, wherein the update flag generation circuit generates the update flag which is enabled when the update pulse is generated, and generates the update flag which is disabled when the synchronization temperature code and the temperature code are the same.

14. The semiconductor system according to claim 12, wherein the semiconductor device further comprises:

an update flag synchronization circuit configured to output the update flag as the synchronization update flag when the internal command is generated.

15. A semiconductor system comprising:

a controller;

a semiconductor device configured to update a synchronization temperature code with a temperature code when the temperature code changes, and apply the synchronization temperature code to the controller in synchronization with an internal command; and

a temperature sensor configured to generate the temperature code which corresponds to a temperature of a region around the semiconductor device.

16. The semiconductor system according to claim 15, wherein the semiconductor device comprises:

a command decoder configured to receive and decode a command outputted by the controller, and generate the internal command to perform a preset operation.

17. The semiconductor system according to claim 15, wherein the semiconductor device comprises:

an update pulse generation circuit configured to generate an update pulse when the temperature code changes;

a command latch signal generation circuit configured to generate a command latch signal from the temperature code in response to the internal command;

an update latch signal generation circuit configured to generate an update latch signal from the temperature code in response to the update pulse; and

a temperature code output circuit configured to generate the synchronization temperature code from the command latch signal in response to an output control pulse.

18. The semiconductor system according to claim 15, wherein the semiconductor device is further configured to generate a synchronization update flag which is enabled for a period in which the synchronization temperature code is updated, and apply the synchronization update flag to the controller in synchronization with the internal command.

19. A semiconductor device comprising:

an update pulse generation circuit configured to generate an update pulse when a temperature code changes;

a command latch signal generation circuit configured to generate a command latch signal from the temperature code in response to an internal command;

an update latch signal generation circuit configured to generate an update latch signal from the temperature code in response to the update pulse; and

a temperature code output circuit configured to generate a synchronization temperature code from the command latch signal in response to an output control pulse.

20. The semiconductor device according to claim 19, further comprising:

a command decoder configured to receive and decode a command, and generate the internal command to perform a preset operation.

21. The semiconductor device according to claim 20, wherein the preset operation is set as a mode register read operation, and the internal command is set as a mode register read command.

22. The semiconductor device according to claim 19, further comprising:

an output control pulse generation circuit configured to generate the output control pulse based on a comparison between the command latch signal and the update latch signal.

23. The semiconductor device according to claim 22, wherein the output control pulse generation circuit generates the output control pulse when the command latch signal and the update latch signal are the same.

24. The semiconductor device according to claim 19, further comprising:

an update flag generation circuit configured to generate an update flag which is enabled when the update pulse is generated, and generate the update flag which is disabled when the synchronization temperature code and the temperature code are the same.

25. The semiconductor device according to claim 20, further comprising:

an update flag synchronization circuit configured to output the update flag as a synchronization update flag when the internal command is generated.