Memory management method, memory control circuit unit and memory storage device

• US 10,490,283 B2
• Filed: 12/04/2017
• Issued: 11/26/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Hu, Chun-Yang
• Primary Examiner(s): Cho, Sung Il
• Application Number:
  US15/831,319
• Publication Number:
  US 20190103163A1
• Time in Patent Office: 722 Days
• Field of Search: 365218
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: performing a single-layer erasing operation on one of physical erasing units; performing a multi-layer erasing operation on another one of the physical erasing units; and performing a wear leveling operation based on the one and the another one of the physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.

Claims

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, the memory management method comprising:

performing a single layer erasing operation on one of the plurality of physical erasing units for n times;

performing a multi-layer erasing operation on another one of the plurality of physical erasing units for n times;

recording a wear value for each of the plurality of physical erasing units;

updating the wear value of the plurality of physical erasing units according to a type of the erasing operation performed on the plurality of physical erasing units, wherein if the single layer erasing operation is performed on a first physical erasing unit of the plurality of physical erasing units, a wear value corresponding to the first physical erasing unit is updated according to a first parameter corresponding to the single layer erasing operation, and if the multi-layer erasing operation is performed on the first physical erasing unit, a wear value corresponding to the first physical erasing unit is updated according to a second parameter corresponding to the multi-layer erasing operation, and the second parameter is no less than the first parameter; and

performing a wear leveling operation on the one and the another one of the physical erasing units according to the wear value of the plurality of physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.

2. The memory management method according to claim 1, further comprising:

establishing a wear table, and recording the wear value of the plurality of physical erasing units in the wear table.

3. The memory management method according to claim 1, further comprising:

recording a single layer erasing count for each of the plurality of physical erasing units; and

recording a multi-layer erasing count for each of the plurality of physical erasing units.

4. The memory management method according to claim 3, wherein the step of updating the wear value of the plurality of physical erasing units according to the type of the erasing operation performed on the plurality of physical erasing units comprises:

obtaining a wear value of the plurality of physical erasing units according to the single layer erasing count and the multi-layer erasing count of the plurality of physical erasing units,

wherein the wear value of the first physical erasing unit is obtained by adding up a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single layer erasing count of the first physical erasing unit by the first parameter, and the second wear value is obtained by multiplying the multi-layer erasing count of the first physical erasing units by the second parameter.

5. The memory management method according to claim 1, further comprising:

adjusting a ratio of the second parameter to the first parameter dynamically according to an erasing count of the plurality of physical erasing units.

6. The memory management method according to claim 1, further comprising:

at least grouping the plurality of physical erasing units into a data area and a free area,

wherein the step of performing the wear leveling operation according to the wear value of the plurality of physical erasing units comprises;

selecting a second physical erasing unit from the physical erasing units from the data area, wherein a wear value of the second physical erasing unit is smaller than a wear value of other physical erasing unit among the physical erasing units in the data area;

selecting a third physical erasing unit from the physical erasing units from the free area, wherein a wear value of the third physical erasing unit is larger than the wear value of the other physical erasing unit among the physical erasing units in the free area;

copying a data in the second physical erasing unit to the third physical erasing unit, associating the third physical erasing unit to the data area, and associating the second physical erasing unit to the free area.

7. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, the memory management method comprising:

recording a wear value for each of the plurality of physical erasing units;

using a first programming mode to program a first physical erasing unit among the plurality of physical erasing units to store a single bit in each memory cell of the first physical erasing unit and updating a wear value corresponding to the first physical erasing unit according to a first parameter and a single layer erasing count corresponding to the first physical erasing unit; and

using a second programming mode to program the first physical erasing unit to store a plurality of bits in each memory cell of the first physical erasing unit and updating the wear value corresponding to the first physical erasing unit according to a second parameter and a multi-layer erasing count corresponding to the first physical erasing unit.

8. The memory management method according to claim 7, further comprises:

updating the single layer erasing count corresponding to the first physical erasing unit after an erasing operation is performed on the first physical erasing unit and the first physical erasing unit stores the single bit;

updating the multi-layer erasing count corresponding to the first physical erasing unit after the erasing operation is performed on the first physical erasing unit and the first physical erasing unit stores the plurality of bits; and

obtaining the wear value corresponding to the first physical erasing unit according to the single layer erasing count and the multi-layer erasing count,

wherein the wear value corresponding to the first physical erasing unit is obtained by adding up a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single layer erasing count by the first parameter, and the second sub-wear value is obtained by multiplying the multi-layer erasing count by the second parameter.

9. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, the memory control circuit unit comprising:

a host interface, coupled to a host system;

a memory interface, coupled to the rewritable non-volatile memory module; and

a memory management circuit, coupled to the host interface and the memory interface,

wherein the memory management circuit performs a single layer erasing operation on one of the plurality of physical erasing units for n times,

wherein the memory management circuit further performs a multi-layer erasing operation on another one of the plurality of physical erasing units for n times,

wherein the memory management circuit further records a wear value for each of the plurality of physical erasing units,

wherein the memory management circuit further updates the wear value of the plurality of physical erasing units according to a type of the erasing operation performed on the plurality of physical erasing units,

wherein if the single layer erasing operation is performed on a first physical erasing unit among the plurality of physical erasing units, a wear value corresponding to the first physical erasing unit is updated according to a first parameter corresponding to the single layer erasing operation, and if the multi-layer erasing operation is performed on the first physical erasing unit, a wear value corresponding to the first physical erasing unit is updated according to a second parameter corresponding to the multi-layer erasing operation, and the second parameter is no less than the first parameter,

wherein the memory management circuit further performs a wear leveling operation on the one and the another one of the physical erasing units according to the wear value of the plurality of physical erasing units,

wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.

10. The memory control circuit unit according to claim 9, wherein the memory management circuit further establishes a wear table, and recording the wear value of the plurality of physical erasing units in the wear table.

11. The memory control circuit unit according to claim 9, wherein the memory management circuit further records a single layer erasing count for each of the plurality of physical erasing units, and records a multi-layer erasing count for each of the plurality of physical erasing units.

12. The memory control circuit unit according to claim 11, wherein in the operation of updating the wear value of the plurality of physical erasing units according to the type of the erasing operation performed on the plurality of physical erasing units, the memory management circuit generates the wear value of the plurality of physical erasing units according to the single layer erasing count and the multi-layer erasing count of the plurality of physical erasing units,

wherein the wear value of the first physical erasing unit is obtained by adding up a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single layer erasing count of the first physical erasing unit by the first parameter, and the second sub-wear value is obtained by multiplying the multi-layer erasing count of the first physical erasing unit by the second parameter.

13. The memory control circuit unit according to claim 9, wherein the memory management circuit further adjusts a ratio of the second parameter to the first parameter dynamically according to an erasing count of the plurality of physical erasing units.

14. The memory control circuit unit according to claim 9, wherein the memory management circuit further at least groups the plurality of physical erasing units into a data area and a free area,

wherein in the operation of performing the wear leveling operation according to the wear value of the plurality of physical erasing units, the memory management circuit selects a second physical erasing unit from the physical erasing units from the data area, selects a third physical erasing unit from the physical erasing units from the free area, copies a data in the second physical erasing unit to the third physical erasing unit, associates the third physical erasing unit to the data area, and associates the second physical erasing unit to the free area,

wherein a wear value of the second physical erasing unit is smaller than a wear value of other physical erasing unit in the physical erasing units in the data area,

wherein a wear value of the third physical erasing unit is larger than the wear value of the other physical erasing unit in the physical erasing units in the free area.

15. A memory storage device, comprising:

a connecting interface unit, coupled to a host system;

a rewritable non-volatile memory module, comprising a plurality of physical erasing units; and

a memory control circuit unit, coupled to the connecting interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit performs a single layer erasing operation on one of the plurality of physical erasing units for n times,

wherein the memory control circuit unit further performs a multi-layer erasing operation on another one of the plurality of physical erasing units for n times,

wherein the memory control circuit unit records a wear value for each of the plurality of physical erasing units,

wherein the memory control circuit unit further updates the wear value of the plurality of physical erasing units according to a type of the erasing operation performed on the plurality of physical erasing units,

wherein if the single layer erasing operation is performed on a first physical erasing unit among the plurality of the physical erasing units, a wear value corresponding to the first physical erasing unit is updated according to a first parameter corresponding to the single layer erasing operation, and if the multi-layer erasing operation is performed on the first physical erasing unit, the wear value corresponding to the first physical erasing unit is updated according to a second parameter corresponding to the multi-layer erasing operation, and the second parameter is no less than the first parameter,

wherein the memory control circuit unit further performs a wear leveling operation on the one and the another one of the physical erasing units according to the wear value of the plurality of the physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.

16. The memory storage device according to claim 15, wherein the memory control circuit unit further establishes a wear table and records the wear value of the plurality of physical erasing units in the wear table.

17. The memory storage device according to claim 15, wherein the memory control circuit unit further records a single layer erasing count for each of the plurality of physical erasing units, and records a multi-layer erasing count for each of the plurality of physical erasing units.

18. The memory storage device according to claim 15, wherein in the operation of updating the wear value of the plurality of physical erasing units according to the type of erasing operation performed on the plurality of physical erasing units, the memory control circuit unit generates the wear value of the plurality of physical erasing units according to the single layer erasing count and the multi-layer erasing count of the plurality of physical erasing units,

wherein the wear value of the first physical erasing unit is obtained by adding up a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single layer erasing count of the first physical erasing unit by the first parameter, and the second sub-wear value is obtained by multiplying the multi-layer erasing count of the first physical erasing unit by the second parameter.

19. The memory storage device according to claim 17, wherein the memory control circuit unit further adjusts a ratio of the second parameter to the first parameter dynamically according to an erasing count of the plurality of physical erasing units.

20. The memory storage device according to claim 17, wherein the memory control circuit unit further at least groups the plurality of physical erasing units into a data area and a free area,

wherein in the operation of performing the wear leveling operation according to the wear value of the plurality of physical erasing units, the memory control circuit unit selects a second physical erasing unit from the physical erasing units from the data area, selects a third physical erasing unit from the physical erasing units from the free area, copies a data in the second physical erasing unit to the third physical erasing unit, associates the third physical erasing unit to the data area, and associates the second physical erasing unit to the free area,

wherein a wear value of the second physical erasing unit is smaller than a wear value of other physical erasing unit in the physical erasing units in the data area,

wherein a wear value of the third physical erasing unit is larger than the wear value of the other physical erasing unit in the physical erasing units in the free area.