Methods of cutting metal gates and structures formed thereof

• US 10,490,458 B2
• Filed: 01/02/2018
• Issued: 11/26/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Perng, Tsu-Hsiu, Yang, Kai-Chieh, Lin, Zhi-Chang, Tsai, Teng-Chun, Wu, Wei-Hao
• Primary Examiner(s): Hall, Victoria K.
• Application Number:
  US15/859,893
• Publication Number:
  US 20190103323A1
• Time in Patent Office: 693 Days
• CPC Class Codes: C23C 16/042 using masks
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Claims

1. A method comprising:

forming a dummy gate stack extending over a plurality of semiconductor fins;

forming gate spacers, with the dummy gate stack being between the gate spacers;

forming a contact etch stop layer and an inter-layer dielectric, with the dummy gate stack and the gate spacers being in the contact etch stop layer and the inter-layer dielectric;

replacing the dummy gate stack with a replacement gate stack, wherein the replacement gate stack comprises a first portion and a second portion, and a third portion joining the first portion to the second portion;

selectively depositing a dielectric hard mask over and contacting the inter-layer dielectric, wherein the replacement gate stack is directly underlying a first opening in the dielectric hard mask, wherein as a thickness of the dielectric hard mask increases during the selectively depositing of the dielectric hard mask, the first opening is simultaneously formed in the dielectric hard mask;

etching the third portion of the replacement gate stack to form a second opening between the gate spacers, wherein the second opening separates the first portion of the replacement gate stack from the second portion of the replacement gate stack; and

filling a dielectric material into the second opening.

2. The method of claim 1 further comprising forming an inhibitor film on the replacement gate stack, wherein the dielectric hard mask is prevented from being formed on the inhibitor film.

3. The method of claim 2, wherein the forming the inhibitor film is performed selectively, so that the inhibitor film is formed to overlap the replacement gate stack, and is not formed starting from the inter-layer dielectric.

4. The method of claim 2, wherein the forming the inhibitor film comprises forming plasma polymerized fluorocarbon.

5. The method of claim 1 further comprising recessing the third portion of the replacement gate stack before forming the dielectric hard mask.

6. The method of claim 5, wherein a recess is left by the recessed third portion of the replacement gate stack, and the method further comprises forming a metal layer over and contacting the replacement gate stack using a selective deposition method so that the metal layer is deposited on the replacement gate stack, and is not deposited starting from the inter-layer dielectric, wherein the metal layer extends into the recess.

7. The method of claim 1 further comprising forming a patterned photo resist, wherein the third portion of the replacement gate stack is directly underlying an opening in the patterned photo resist, and the etching the third portion of the replacement gate stack is performed through the opening in the patterned photo resist.

8. A method comprising:

forming an inter-layer dielectric having opposing portions;

forming a replacement gate stack between the opposing portions of the inter-layer dielectric, wherein the replacement gate stack comprises a gate dielectric and a metal gate electrode over the gate dielectric;

planarizing the replacement gate stack and the inter-layer dielectric;

forming an inhibitor film on the replacement gate stack, with at least a portion of the inter-layer dielectric exposed;

selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon; and

etching to remove a portion of the replacement gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

9. The method of claim 8 further comprising, before the portion of the replacement gate stack is removed and after the dielectric hard mask is selectively deposited, removing the inhibitor film.

10. The method of claim 8 further comprising, filling an isolation layer into an opening left by the removed portion of the replacement gate stack, wherein the isolation layer comprises a portion overlapping and contacting the inhibitor film.

11. The method of claim 8, wherein the forming the inhibitor film comprises forming plasma polymerized fluorocarbon.

12. The method of claim 11, wherein the plasma polymerized fluorocarbon comprises both fluorine and carbon, and is substantially free from additional elements other than fluorine and carbon.

13. The method of claim 11, wherein the plasma polymerized fluorocarbon has a carbon percentage between about 30 percent and about 80 percent.

14. The method of claim 8, wherein the selectively depositing the dielectric hard mask comprises depositing a material selected from the group consisting of ZrO₂, HfO₂, Y₂O₃, HfZrO_x, HfSiO_x, zirconium silicate (ZrSiOx), yttrium silicates (YSiO_x), HfZrSiO_x, Al₂O₃, HfAlO_x, ZrAlO_x, La₂O₃, lanthanum silicate (LaSiO_x), ZnO, TiO₂, and combinations thereof.

15. A method comprising:

forming an inter-layer dielectric having opposing portions;

forming a replacement gate stack between the opposing portions of the inter-layer dielectric, wherein the replacement gate stack comprises a gate dielectric and a metal gate electrode over the gate dielectric;

planarizing the replacement gate stack and the inter-layer dielectric;

selectively growing an inhibitor film on the replacement gate stack and not on the inter-layer dielectric; and

selectively depositing a dielectric hard mask on the inter-layer dielectric and not on the inhibitor film.

16. The method of claim 15 further etching a portion of the replacement gate stack, with the dielectric hard mask protecting underlying portions of the inter-layer dielectric in the etching.

17. The method of claim 15 further comprising removing the inhibitor film.

18. The method of claim 15, wherein the inhibitor film includes a portion lower than a top surface of the inter-layer dielectric.

19. The method of claim 15, wherein the forming the inhibitor film comprises forming plasma polymerized fluorocarbon.

20. The method of claim 15, wherein the selectively growing the inhibitor film comprises growing a plasma polymerized fluorocarbon film, wherein the plasma polymerized fluorocarbon film comprises both fluorine and carbon, and is substantially free from additional elements other than fluorine and carbon.