Method for source/drain contact formation in semiconductor devices

• US 10,490,459 B2
• Filed: 08/25/2017
• Issued: 11/26/2019
• Est. Priority Date: 08/25/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Koh, Shao-Ming, Lee, Chen-Ming, Wu, I-Wen, Yang, Fu-Kai, Wang, Jia-Heng, Wang, Mei-Yun
• Primary Examiner(s): Miller, Jami Valentine
• Application Number:
  US15/686,698
• Publication Number:
  US 20190067130A1
• Time in Patent Office: 823 Days
• Field of Search: 257369
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 : Silicon carbide
• CPC Class Codes: H01L 29/161 : including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 : further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/665 : using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7843 : the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 : the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H04B 1/00 : Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
• CPC Class Codes: H04B 3/00 : Line transmission systems combined with near-field transmission systems H04B5/00
• CPC Class Codes: H04H 60/04 : Studio equipment; Interconnection of studios
• CPC Class Codes: H04R 2420/01 : Input selection or mixing for amplifiers or loudspeakers for hearing aids H04R25/43
• CPC Class Codes: H04R 25/43 : Electronic input selection or mixing based on input signal analysis, e.g. mixing or selection between microphone and telecoil or between microphones with different directivity characteristics H04R25/407 takes precedence
• CPC Class Codes: H04R 3/00 : Circuits for transducers , loudspeakers or microphones
• CPC Class Codes: H04R 3/005 : for combining the signals of two or more microphones specially adapted for hearing aids H04R25/407
• CPC Class Codes: H04R 5/02 : Spatial or constructional arrangements of loudspeakers

Abstract

A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a structure that includes;

a substrate;

a first gate structure and a second gate structure over the substrate;

a first source/drain (S/D) feature and a second S/D feature over the substrate, wherein the first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, and the first and second S/D features comprise different materials;

a first dielectric layer over sidewalls of the first and second gate structures and over the first and second S/D features; and

a second dielectric layer over the first dielectric layer;

etching the first and second dielectric layers to expose the first and second S/D features;

doping a p-type dopant into the first and second S/D features; and

after the doping of the p-type dopant, performing a selective etching process to the first and second S/D features, wherein the selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.

2. The method of claim 1, wherein the first S/D feature comprises silicon or silicon-carbon doped with an n-type dopant, and the second S/D feature comprises silicon germanium.

3. The method of claim 2, wherein the n-type dopant is phosphorus or arsenic and the p-type dopant is boron.

4. The method of claim 3, wherein the selective etching process includes a dry etching process using a gas mixture of SF₆, H₂, and CF₄.

5. The method of claim 3, wherein the selective etching process includes a wet etching process using NH₄OH or TMAH.

6. The method of claim 1, wherein the doping of the p-type dopant uses a doping energy ranging from 1 keV to 5 keV and a doping dose of the p-type dopant ranging from 1E15 cm⁻

2 to 1E16 cm<sup>−

2</sup>.

7. The method of claim 1, after the etching of the first and second dielectric layer and before the doping of the p-type dopant, further comprising:

depositing a third dielectric layer over the structure; and

performing an anisotropic etching process to the third dielectric layer to expose the first and second S/D features and to keep a portion of the third dielectric layer over sidewalls of the first and second gate structures.

8. The method of claim 1, after the performing of the selective etching process, further comprising:

annealing the p-type dopant in the second S/D feature.

9. The method of claim 1, before the performing of the selective etching process, further comprising:

annealing the p-type dopant in at least the second S/D feature.

10. The method of claim 1, after the performing of the selective etching process, further comprising:

depositing a metal over remaining portions of the first and second S/D features.

11. The method of claim 10, after the performing of the selective etching process and before the depositing of the metal, further comprising:

forming a first silicide feature over the remaining portion of the first S/D feature; and

forming a second silicide feature over the remaining portion of the second S/D feature.

12. A method of forming a semiconductor device, the method comprising:

providing a structure that includes;

a substrate;

a first gate structure and a second gate structure over the substrate;

a first source/drain (S/D) feature comprising n-type doped silicon adjacent to the first gate structure;

a second S/D feature comprising silicon germanium adjacent to the second gate structure; and

one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features;

etching the one or more dielectric layers to expose the first and second S/D features;

doping a p-type dopant into the first and second S/D features by a same doping process, resulting in a p-type doped portion of the first S/D feature and a p-type doped portion of the second S/D feature; and

after the doping of the p-type dopant, partially etching the first and second S/D features by a same etching process, wherein the etching process recesses the first S/D feature at a faster rate than it recesses the second S/D feature.

13. The method of claim 12, wherein the p-type dopant comprises boron and the doping process uses a doping energy ranging from 1 keV to 5 keV and a doping dose ranging from 1E15 cm⁻

2 to 1E16 cm<sup>−

2</sup>.

14. The method of claim 12, wherein the same etching process completely removes the p-type doped portion of the first S/D feature and partially removes the p-type doped portion of the second S/D feature.

15. The method of claim 12, wherein the same etching process includes dry etching with a gas mixture of SF₆, H₂, and CF₄.

16. The method of claim 12, wherein the same etching process includes wet etching with NH₄OH or TMAH.

17. The method of claim 12, after the partially etching of the first and second S/D features, further comprising:

activating the p-type dopant in the second S/D feature.

18. The method of claim 17, after the activating of the p-type dopant, further comprising:

cleaning a top surface of the first and second S/D features using a dry cleaning process or a wet cleaning process;

forming a first silicide feature over the first S/D feature; and

forming a second silicide feature the second S/D feature.

19. A method of forming a semiconductor device, the method comprising:

providing a structure that includes;

a substrate;

a first source/drain (S/D) feature comprising an n-type doped semiconductor material;

a second S/D feature comprising another semiconductor material different from the n-type doped semiconductor material; and

one or more dielectric layers over the first and second S/D features;

etching the one or more dielectric layers to expose the first and second S/D features;

doping a p-type dopant into the first and second S/D features; and

after the doping of the p-type dopant, recessing the first and second S/D features by a same etching process, wherein the same etching process completely removes a p-type doped portion of the first S/D feature and partially removes a p-type doped portion of the second S/D feature.

20. The method of claim 19, after the recessing of the first and second S/D features, further comprising:

annealing the structure to at least activate the p-type dopant in the second S/D feature.