Wafer-level packaging for enhanced performance
First Claim
1. A method comprising:
- providing a precursor wafer that includes a silicon handle layer, a stop layer, a device layer, and a plurality of first bump structures, wherein;
the device layer has a plurality of input/output (I/O) contacts at a top surface of the device layer;
the plurality of first bump structures are formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;
the stop layer resides underneath the device layer; and
the silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer;
applying a first mold compound over the device layer to encapsulate each of the plurality of first bump structures;
removing substantially the silicon handle layer;
applying a second mold compound to an exposed surface from which the silicon handle layer was removed; and
thinning down the first mold compound to provide a mold wafer, wherein a portion of each of the plurality of first bump structures is exposed.
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Abstract
The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.
235 Citations
22 Claims
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1. A method comprising:
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providing a precursor wafer that includes a silicon handle layer, a stop layer, a device layer, and a plurality of first bump structures, wherein; the device layer has a plurality of input/output (I/O) contacts at a top surface of the device layer; the plurality of first bump structures are formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact; the stop layer resides underneath the device layer; and the silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer; applying a first mold compound over the device layer to encapsulate each of the plurality of first bump structures; removing substantially the silicon handle layer; applying a second mold compound to an exposed surface from which the silicon handle layer was removed; and thinning down the first mold compound to provide a mold wafer, wherein a portion of each of the plurality of first bump structures is exposed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification