×

Wafer-level packaging for enhanced performance

  • US 10,490,471 B2
  • Filed: 05/30/2018
  • Issued: 11/26/2019
  • Est. Priority Date: 07/06/2017
  • Status: Active Grant
First Claim
Patent Images

1. A method comprising:

  • providing a precursor wafer that includes a silicon handle layer, a stop layer, a device layer, and a plurality of first bump structures, wherein;

    the device layer has a plurality of input/output (I/O) contacts at a top surface of the device layer;

    the plurality of first bump structures are formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;

    the stop layer resides underneath the device layer; and

    the silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer;

    applying a first mold compound over the device layer to encapsulate each of the plurality of first bump structures;

    removing substantially the silicon handle layer;

    applying a second mold compound to an exposed surface from which the silicon handle layer was removed; and

    thinning down the first mold compound to provide a mold wafer, wherein a portion of each of the plurality of first bump structures is exposed.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×